公开(公告)号：US09966426B2

公开(公告)日：2018-05-08

申请号：US14853967

申请日：2015-09-14

Applicant: QUALCOMM Incorporated

Inventor： Niranjan Sunil Mudakatte ,  Daeik Daniel Kim ,  David Francis Berdy ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  Chengjie Zuo ,  Mario Francisco Velez ,  Robert Paul Mikulka ,  Jonghae Kim

IPC: H01L23/057 ,  H01L23/48 ,  H01L23/495 ,  H01L49/02 ,  H01L23/522 ,  H01L27/08 ,  H01L23/00

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L24/13 ,  H01L27/0805 ,  H01L28/87 ,  H01L28/91 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13109 ,  H01L2224/94 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10337 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2224/03

Abstract: An augmented capacitor structure includes a substrate and a first capacitor plate of a first conductive layer on the substrate. The augmented capacitor structure also includes an insulator layer on a surface of the first capacitor plate facing away from the substrate and a second capacitor plate. The second capacitor plate includes a second conductive layer on the insulator layer, supported by the first capacitor plate as a first capacitor. A second capacitor electrically is coupled in series with the first capacitor. The first capacitor plate is shared by the first capacitor and the second capacitor as a shared first capacitor plate. An extended first capacitor plate includes a first dummy portion of a third conductive layer and a first dummy via bar extending along the surface of the shared first capacitor plate. The first dummy portion extends along and is supported by the first dummy via bar.

公开(公告)号：US09935166B2

公开(公告)日：2018-04-03

申请号：US13833632

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Lan ,  Chengjie Zuo ,  Changhan Yun ,  David F. Berdy ,  Daeik D. Kim ,  Robert P. Mikulka ,  Mario Francisco Velez ,  Jonghae Kim

IPC: H05K1/16 ,  H01L49/02 ,  G06F17/50 ,  H01L23/498 ,  H01L27/01 ,  H01L23/15 ,  H01L27/12

CPC classification number: H01L28/40 ,  G06F17/5068 ,  H01L23/15 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L27/016 ,  H01L27/12 ,  H01L28/10 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a particular embodiment, a device includes a substrate, a via that extends at least partially through the substrate, and a capacitor. A dielectric of the capacitor is located between the via and a plate of the capacitor, and the plate of the capacitor is external to the substrate and within the device.

公开(公告)号：US20180062617A1

公开(公告)日：2018-03-01

申请号：US15247803

申请日：2016-08-25

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie Yun ,  Je-Hsiung Lan ,  Chengjie Zuo ,  David Berdy ,  Jonghae Kim ,  Mario Velez ,  Niranjan Sunil Mudakatte ,  Shiqun Gu

IPC: H03H9/205 ,  H01L41/332 ,  H03H9/54

CPC classification number: H03H9/205 ,  H01L41/332 ,  H03H3/04 ,  H03H9/173 ,  H03H9/54 ,  H03H2003/021 ,  H03H2003/0435 ,  H03H2003/0442 ,  H03H2003/0471

Abstract: A single-die multi-FBAR (film bulk acoustic resonator) device includes multiple FBARs having different resonant frequencies formed over a single substrate. The FBARs include piezoelectric layers having different thicknesses but with upper electrodes formed at a same height over the substrate, lower electrodes at different heights over the substrate, and different sized air gaps separating the lower electrodes from the substrate.

公开(公告)号：US09906318B2

公开(公告)日：2018-02-27

申请号：US14682023

申请日：2015-04-08

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Daeik Daniel Kim ,  David Francis Berdy ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  Robert Paul Mikulka ,  Mario Francisco Velez ,  Jonghae Kim ,  Matthew Michael Nowak ,  Ryan Scott C. Spring ,  Xiangdong Zhang

IPC: H04J1/00 ,  H04J1/08 ,  H03H7/46 ,  H04B1/00

CPC classification number: H04J1/08 ,  H03H7/465 ,  H03H2240/00 ,  H03H2250/00 ,  H04B1/0057 ,  H04B1/006 ,  H04B1/0064

Abstract: An apparatus is disclosed that includes a frequency multiplexer circuit coupled to an input node and configured to receive an input signal via the input node. The frequency multiplexer circuit comprises a first filter circuit, a second filter circuit, and a third filter circuit. The apparatus also includes a switching circuit that is configurable to couple at least two of a first output of the first filter circuit, a second output of the second filter circuit, or a third output of the third filter circuit to a single output port.

公开(公告)号：US20180026666A1

公开(公告)日：2018-01-25

申请号：US15216615

申请日：2016-07-21

Applicant: QUALCOMM Incorporated

Inventor： Changhan Yun ,  Chengjie Zuo ,  Mario Velez ,  Niranjan Sunil Mudakatte ,  Shiqun Gu ,  Jonghae Kim ,  David Berdy

IPC: H04B1/16 ,  H01L21/48 ,  H01L23/498 ,  H01L23/66 ,  H01L27/01 ,  H01L49/02

CPC classification number: H04B1/1638 ,  H01F17/0013 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5223 ,  H01L23/64 ,  H01L23/66 ,  H01L24/19 ,  H01L24/20 ,  H01L27/01 ,  H01L28/10 ,  H01L28/40 ,  H01L2223/6616 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2223/6688 ,  H01L2224/04105 ,  H01L2224/24195 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/15153 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19105 ,  H04B1/006 ,  H05K1/165 ,  H05K1/185 ,  H05K3/4605 ,  H05K2201/09536 ,  H05K2201/097

Abstract: In an illustrative example, an apparatus includes a passive-on-glass (POG) device integrated within a glass substrate. The apparatus further includes a semiconductor die integrated within the glass substrate.

公开(公告)号：US20170331445A1

公开(公告)日：2017-11-16

申请号：US15151351

申请日：2016-05-10

Applicant: QUALCOMM Incorporated

Inventor： Yunfei Ma ,  Chengjie Zuo ,  David Francis Berdy ,  Daeik Daniel Kim ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  Mario Francisco Velez ,  Niranjan Sunil Mudakatte ,  Robert Paul Mikulka ,  Jonghae Kim

IPC: H03H7/38 ,  H03H7/40

CPC classification number: H03H7/38 ,  H03H7/40 ,  H04B1/0458

Abstract: A tunable matching network is disclosed. In a particular example, the matching network includes at least one first inductor in a signal path of the matching network. The matching network includes at least one second inductor outside of the signal path. The matching network includes one or more switches coupled to the at least one second inductor. The one or more switches are configured to selectively enable mutual coupling of the at least one first inductor and the at least one second inductor.

公开(公告)号：US09768109B2

公开(公告)日：2017-09-19

申请号：US14861958

申请日：2015-09-22

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Daeik Daniel Kim ,  Matthew Michael Nowak ,  Jonghae Kim ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  David Francis Berdy

IPC: H01L23/498 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/304 ,  H01L27/088 ,  H01L27/12 ,  H01L23/66 ,  H01L21/306

CPC classification number: H01L27/1203 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/76251 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/49894 ,  H01L23/528 ,  H01L23/66 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1222 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1266 ,  H01L29/1087 ,  H01L29/66772

Abstract: An integrated circuit (IC) includes a first semiconductor device on a glass substrate. The first semiconductor device includes a first semiconductive region of a bulk silicon wafer. The IC includes a second semiconductor device on the glass substrate. The second semiconductor device includes a second semiconductive region of the bulk silicon wafer. The IC includes a through substrate trench between the first semiconductive region and the second semiconductive region. The through substrate trench includes a portion disposed beyond a surface of the bulk silicon wafer.

公开(公告)号：US09634640B2

公开(公告)日：2017-04-25

申请号：US13887568

申请日：2013-05-06

Applicant: QUALCOMM Incorporated

Inventor： Chengjie Zuo ,  Daeik D. Kim ,  Je-Hsiung Lan ,  Jonghae Kim ,  Mario Francisco Velez ,  Changhan Yun ,  David F. Berdy ,  Robert P. Mikulka ,  Matthew M. Nowak ,  Xiangdong Zhang ,  Puay H. See

IPC: H03H7/46

CPC classification number: H03H7/461 ,  H03H3/00 ,  H03H7/0115 ,  H03H7/463 ,  Y10T29/49016

Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.

公开(公告)号：US20170084628A1

公开(公告)日：2017-03-23

申请号：US14858203

申请日：2015-09-18

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel Kim ,  Changhan Hobie Yun ,  Je-Hsiung Jeffrey Lan ,  Jonghae Kim ,  Matthew Michael Nowak

IPC: H01L27/12 ,  H01L21/762

CPC classification number: H01L27/1203 ,  H01L21/76256 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76283 ,  H01L21/84 ,  H01L21/86

Abstract: Substrate-transferred, deep trench isolation silicon-on-insulator (SOI) semiconductor devices formed from bulk semiconductor wafers are disclosed. In this regard, a bulk semiconductor wafer is provided that includes a bulk body, one or more transistors formed in the bulk body, and deep trenches formed between the transistors formed in the bulk body to provide isolation between the transistors. To prevent the bulk body from electrically interconnecting the transistors, the bulk body is thinned near, at, or beyond a back side of the deep trenches formed in the bulk body to form separate bulk bodies for each transistor isolated by the deep trenches. An insulation substrate is bonded to the bulk semiconductor device to form an SOI wafer. In this manner, residual bulk bodies of the transistors in the SOI wafer are isolated between the deep trenches and the insulation substrate to reduce or avoid leakage current between transistors.

公开(公告)号：US09601607B2

公开(公告)日：2017-03-21

申请号：US14225836

申请日：2014-03-26

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Daeik Daniel Kim ,  Bin Yang ,  Jonghae Kim ,  Daniel Wayne Perry

IPC: H03K17/687 ,  H01L29/739 ,  G05F3/16 ,  H01L27/07

CPC classification number: H01L29/7393 ,  G05F3/16 ,  H01L27/0705

Abstract: A method includes biasing a first gate voltage to enable unipolar current to flow from a first region of a transistor to a second region of the transistor according to a field-effect transistor (FET)-type operation. The method also includes biasing a body terminal to enable bipolar current to flow from the first region to the second region according to a bipolar junction transistor (BJT)-type operation. The unipolar current flows concurrently with the bipolar current to provide dual mode digital and analog device in complementary metal oxide semiconductor (CMOS) technology.