公开(公告)号：US09853446B2

公开(公告)日：2017-12-26

申请号：US14838034

申请日：2015-08-27

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Eugene Robert Worley ,  Ratibor Radojcic ,  Urmi Ray

IPC: H02H9/04 ,  H01L23/48 ,  H01L23/60 ,  H01L23/62 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L23/48 ,  H01L23/60 ,  H01L23/62 ,  H01L27/0255 ,  H01L27/0292 ,  H01L27/0296 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H02H9/044 ,  H01L2924/00012

Abstract: An intergrated circuit (IC) package includes a die, a package substrate coupled to the die, and a first electrostatic discharge (ESD) protection component coupled to the package substrate, where the first electrostatic discharge (ESD) protection component is configured to provide package level electrostatic discharge (ESD) protection. In some implementations, the first electrostatic discharge (ESD) protection component is embedded in the package substrate. In some implementations, the die includes an internal electrostatic discharge (ESD) protection component configured to provide die level electrostatic discharge (ESD) protection. In some implementations, the internal electrostatic discharge (ESD) protection component and the first electrostatic discharge (ESD) protection component are configured to provide cumulative electrostatic discharge (ESD) protection for the die.

公开(公告)号：US09773741B1

公开(公告)日：2017-09-26

申请号：US15239588

申请日：2016-08-17

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Yang Du ,  William Xia

IPC: H01L23/20 ,  H01L23/48 ,  H01L23/52 ,  H01L23/00 ,  H01L23/528 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/564 ,  H01L21/2007 ,  H01L23/291 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/13 ,  H01L24/29 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/2745 ,  H01L2224/27622 ,  H01L2224/29186 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81002 ,  H01L2224/81143 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81895 ,  H01L2224/83002 ,  H01L2224/83143 ,  H01L2224/83193 ,  H01L2224/83203 ,  H01L2224/83862 ,  H01L2224/83896 ,  H01L2224/9205 ,  H01L2224/9211 ,  H01L2224/94 ,  H01L2225/06548 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2224/27 ,  H01L2924/00

Abstract: An apparatus includes a first component layer. The component layer includes a first semiconductor device. The apparatus further includes a first hydrophilic layer and a first hydrophobic layer. The first hydrophobic layer is positioned between the first component layer and the first hydrophilic layer. The apparatus further includes a first contact extending through the first hydrophobic layer and the first hydrophilic layer.

公开(公告)号：US09577025B2

公开(公告)日：2017-02-21

申请号：US14181522

申请日：2014-02-14

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Ryan David Lane ,  Glenn David Raskin ,  Shree Krishna Pandey

IPC: H01L49/02 ,  H01L23/00 ,  H01L23/538 ,  H01L23/522

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/02371 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2924/1205

Abstract: Some features pertain to an integrated device that includes a substrate, several metal layers coupled to the substrate, several dielectric layers coupled to the substrate, and a redistribution portion coupled to one of the metal layers. The redistribution portion includes a first metal redistribution layer, an insulation layer coupled to the first metal redistribution layer, and a second metal redistribution layer coupled to the insulation layer. The first metal redistribution layer, the insulation layer, and the second metal redistribution layer are configured to operate as a capacitor in the integrated device. In some implementations, the capacitor is a metal-insulator-metal (MIM) capacitor.

Abstract translation: 一些特征涉及包括衬底，耦合到衬底的几个金属层，耦合到衬底的几个电介质层和耦合到金属层之一的再分配部分的集成器件。 再分配部分包括第一金属再分布层，耦合到第一金属再分布层的绝缘层和耦合到绝缘层的第二金属再分配层。 第一金属再分布层，绝缘层和第二金属再分配层被配置为在集成器件中作为电容器工作。 在一些实施方案中，电容器是金属 - 绝缘体 - 金属（MIM）电容器。

公开(公告)号：US09401353B2

公开(公告)日：2016-07-26

申请号：US14454851

申请日：2014-08-08

Applicant: QUALCOMM Incorporated

Inventor： Vidhya Ramachandran ,  Shiqun Gu

IPC: H01L27/02 ,  H01L21/48 ,  H01L23/64 ,  H01L23/48 ,  H01L49/02

CPC classification number: H01L27/0288 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5223 ,  H01L23/642 ,  H01L25/0652 ,  H01L25/16 ,  H01L27/0255 ,  H01L28/90 ,  H01L2224/16227 ,  H01L2924/15311

Abstract: An integrated interposer includes an interposer substrate including at least a first portion of a 3D passive device within an active region of the interposer substrate. The integrated interposer also includes an inter-conductive dielectric layer on an active surface of the active region of the interposer substrate, the inter-conductive dielectric layer including at least a second portion of the 3D passive device. The integrated interposer further includes a contact layer coupled to the 3D passive devices and configured to couple at least one die to the integrated interposer. The integrated interposer also includes at least one through via coupled to the contact layer and extending through the interposer substrate to a passive surface of the interposer substrate. The integrated interposer further includes an interconnect layer on the passive surface of the interposer substrate and coupled to the at least one through via.

Abstract translation: 集成插入器包括插入器基板，其包括在内插器基板的有源区域内的3D无源器件的至少第一部分。 该集成插入器还包括在该插入器基板的有源区域的有源表面上的导电介电层，该导电介质层至少包括该3D无源器件的第二部分。 集成中介层还包括耦合到3D无源器件并被配置为将至少一个管芯耦合到集成插入器的接触层。 集成插入器还包括至少一个通孔，其连接到接触层并且延伸穿过插入器衬底到内插器衬底的无源表面。 集成插入器还包括在插入器基板的被动表面上并且耦合到至少一个通孔的互连层。

公开(公告)号：US20150228556A1

公开(公告)日：2015-08-13

申请号：US14274517

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Jae Sik Lee ,  Hong Bok We ,  Dong Wook Kim ,  Shiqun Gu

IPC: H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L23/50

CPC classification number: H01L23/481 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/49827 ,  H01L23/50 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/1533

Abstract: Some novel features pertain to an integrated device that includes an encapsulation layer, a via structure traversing the encapsulation layer, and a pad. The via structure includes a via that includes a first side, a second side, and a third side. The via structure also includes a barrier layer surrounding at least the first side and the third side of the via. The pad is directly coupled to the barrier layer of the via structure. In some implementations, the integrated device includes a first dielectric layer coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a substrate coupled to a first surface of the encapsulation layer. In some implementations, the integrated device includes a first die coupled to the substrate, where the encapsulation layer encapsulates the first die. In some implementations, the via includes a portion configured to operate as a pad.

Abstract translation: 一些新颖的特征涉及包括封装层，穿过封装层的通孔结构和焊盘的集成器件。 通孔结构包括通孔，其包括第一侧，第二侧和第三侧。 通孔结构还包括至少围绕通孔的第一侧和第三侧的阻挡层。 焊盘直接耦合到通孔结构的阻挡层。 在一些实施方案中，集成器件包括耦合到封装层的第一表面的第一介电层。 在一些实施方案中，集成器件包括耦合到封装层的第一表面的衬底。 在一些实施方案中，集成器件包括耦合到衬底的第一管芯，其中封装层封装第一管芯。 在一些实施方式中，通孔包括被配置为作为垫进行操作的部分。

公开(公告)号：US09087765B2

公开(公告)日：2015-07-21

申请号：US13839816

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Dexter Tamio Chun ,  Jungwon Suh ,  Urmi Ray ,  Shiqun Gu

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/16 ,  H01L23/14 ,  H01L23/31 ,  H01L23/373 ,  H01L23/15

CPC classification number: H01L23/16 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/3737 ,  H01L23/49816 ,  H01L23/49827 ,  H01L25/0652 ,  H01L25/18 ,  H01L2224/13 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81203 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/1436 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/11

Abstract: An integrated circuit package is disclosed that includes a first-pitch die and a second-pitch die. The second-pitch die interconnects to the second-pitch substrate through second-pitch substrates. The first-pitch die interconnects through first-pitch interconnects to an interposer adapter. The pitch of the first-pitch interconnects is too fine for the second-pitch substrate. But the interposer adapter interconnects through second-pitch interconnects to the second-pitch substrate and includes through substrate vias so that I/O signaling between the first-pitch die and the second-pitch die can be conducted through the second-pitch substrate and through the through substrate vias in the interposer adapter.

Abstract translation: 公开了一种集成电路封装，其包括第一间距管芯和第二间距管芯。 第二间距模具通过第二间距基板与第二间距基板相互连接。 第一间距模具通过第一间距互连件互连到插入器适配器。 第一节距互连的间距对于第二间距衬底来说太细了。 但是插入器适配器通过第二间距互连件连接到第二间距衬底并且包括通过衬底通孔，使得第一间距管芯和第二间距管芯之间的I / O信号可以通过第二间距衬底并且通过 贯穿衬底通孔插入插座适配器中。

公开(公告)号：US09024315B2

公开(公告)日：2015-05-05

申请号：US13800976

申请日：2013-03-13

Applicant: QUALCOMM Incorporated

Inventor： Hongjun Yao ,  Michael Laisne ,  Matthew M Nowak ,  Glen T Kim ,  Mark C Chan ,  Shiqun Gu

IPC: H01L23/58 ,  H01L21/66

CPC classification number: H01L22/32 ,  G01R31/31717 ,  H01L22/14 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/00

Abstract: An integrated circuit product package configured to continuity testing is described. The integrated circuit product package includes a package substrate. The package substrate includes internal routing connections. The integrated circuit product package also includes a semiconductor die coupled to the package substrate. The semiconductor die includes input/output (I/O) pins and switches. The switches selectively coupled the I/O pins to facilitate a daisy chain connection. The daisy chain connection includes circuitry fabricated on the semiconductor die, more than two of the internal routing connections, more than two of the I/O pins and at least one switch.

Abstract translation: 描述了被配置为连续性测试的集成电路产品包。 集成电路产品封装包括封装衬底。 封装衬底包括内部路由连接。 集成电路产品封装还包括耦合到封装衬底的半导体管芯。 半导体管芯包括输入/​​输出（I / O）引脚和开关。 开关选择性地耦合I / O引脚以便于菊花链连接。 菊花链连接包括在半导体芯片上制造的电路，多于两个的内部路由连接，多于两个的I / O引脚和至少一个开关。

公开(公告)号：US20150048465A1

公开(公告)日：2015-02-19

申请号：US14499027

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Rongtian Zhang ,  Vidhya Ramachandran ,  Dong Wook Kim

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L23/3121 ,  H01L23/552 ,  H01L23/645 ,  H01L27/222 ,  H01L27/228 ,  H01L43/02 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2924/0002 ,  H01L2924/1435 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Some implementations provide a die that includes a magnetoresistive random access memory (MRAM) cell array that includes several MRAM cells. The die also includes a first ferromagnetic layer positioned above the MRAM cell array, a second ferromagnetic layer positioned below the MRAM cell array, and several vias positioned around at least one MRAM cell. The via comprising a ferromagnetic material. In some implementations, the first ferromagnetic layer, the second ferromagnetic layer and the several vias define a magnetic shield for the MRAM cell array. The MRAM cell may include a magnetic tunnel junction (MTJ). In some implementations, the several vias traverse at least a metal layer and a dielectric layer of the die. In some implementations, the vias are through substrate vias. In some implementations, the ferromagnetic material has high permeability and high B saturation.

Abstract translation: 一些实施方案提供了包括包括几个MRAM单元的磁阻随机存取存储器（MRAM）单元阵列的管芯。 芯片还包括位于MRAM单元阵列上方的第一铁磁层，位于MRAM单元阵列下方的第二铁磁层和位于至少一个MRAM单元周围的几个通孔。 通孔包括铁磁材料。 在一些实施方案中，第一铁磁层，第二铁磁层和几个通孔限定用于MRAM单元阵列的磁屏蔽。 MRAM单元可以包括磁性隧道结（MTJ）。 在一些实施方案中，几个通孔至少穿过管芯的金属层和电介质层。 在一些实施方案中，通孔通过衬底通孔。 在一些实施方案中，铁磁材料具有高磁导率和高B饱和度。

公开(公告)号：US08884408B2

公开(公告)日：2014-11-11

申请号：US13777475

申请日：2013-02-26

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Rongtian Zhang ,  Vidhya Ramachandran ,  Dong Wook Kim

IPC: H01L23/552 ,  H01L43/02

Abstract: Some implementations provide a die that includes a magnetoresistive random access memory (MRAM) cell array that includes several MRAM cells. The die also includes a first ferromagnetic layer positioned above the MRAM cell array, a second ferromagnetic layer positioned below the MRAM cell array, and several vias positioned around at least one MRAM cell. The via comprising a ferromagnetic material. In some implementations, the first ferromagnetic layer, the second ferromagnetic layer and the several vias define a magnetic shield for the MRAM cell array. The MRAM cell may include a magnetic tunnel junction (MTJ). In some implementations, the several vias traverse at least a metal layer and a dielectric layer of the die. In some implementations, the vias are through substrate vias. In some implementations, the ferromagnetic material has high permeability and high B saturation.

公开(公告)号：US20140225280A1

公开(公告)日：2014-08-14

申请号：US13766218

申请日：2013-02-13

Applicant: QUALCOMM INCORPORATED

Inventor： Brian M. Henderson ,  Shiqun Gu

IPC: H01L23/498 ,  H01L21/50

CPC classification number: H01L21/50 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/525 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2224/13099

Abstract: A semiconductor device includes a die coupled to a substrate, a first memory device coupled to a surface of the die opposite the substrate and a coupling device coupled between the surface of the die opposite the substrate and a second memory device such that the second memory device at least partially overlaps the first memory device. Also disclosed is method of mounting first and second memory devices on a die in an at least partially overlapping manner.

Abstract translation: 半导体器件包括耦合到衬底的管芯，耦合到与衬底相对的管芯的表面的第一存储器件和耦合在与衬底相对的管芯的表面之间的耦合器件和第二存储器件 至少部分地与第一存储器件重叠。 还公开了以至少部分重叠的方式将第一和第二存储器件安装在管芯上的方法。