公开(公告)号：US20190391325A1

公开(公告)日：2019-12-26

申请号：US16438067

申请日：2019-06-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tetsuya IIDA ,  Yasutaka NAKASHIBA

IPC: G02B6/036 ,  G02B6/42

Abstract: The semiconductor device includes an optical waveguide WG1 formed in a planar manner, and a three-dimensional optical waveguide WG2 optically connected with the optical waveguide WG1 and including a curved shape.

公开(公告)号：US20190273066A1

公开(公告)日：2019-09-05

申请号：US16278927

申请日：2019-02-19

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Shinichi KUWABARA ,  Yasutaka NAKASHIBA ,  Tetsuya IIDA

IPC: H01L25/065 ,  H02K11/33 ,  H01L23/31 ,  H01L23/495 ,  H01L23/522 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L49/02

Abstract: A semiconductor device includes a first semiconductor chip having a first inductor element and a second inductor element on a first main surface side, a second semiconductor chip having a third inductor element on a second main surface side, and a third semiconductor chip having a fourth inductor element on a third main surface side. The first and second inductor elements are arranged to be separated from each other in a first direction of the first main surface, the first and second main surfaces face each other, and the first and third inductor elements overlap each other. The first and third main surfaces face each other, the second and fourth inductor elements overlap each other, and a creepage distance between the second and third semiconductor chips is larger than a separation distance between the second and third semiconductor chips.

公开(公告)号：US20180182751A1

公开(公告)日：2018-06-28

申请号：US15796816

申请日：2017-10-29

Applicant: Renesas Electronics Corporation

Inventor： Shinichi UCHIDA ,  Takafumi KURAMOTO ,  Yasutaka NAKASHIBA

IPC: H01L27/06 ,  H01L27/12 ,  H01L29/93 ,  H01L29/06 ,  H01L23/522 ,  H01L23/528 ,  H01L21/84 ,  H01L29/66

CPC classification number: H01L27/0629 ,  H01L21/84 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/66174 ,  H01L29/93 ,  H01L29/94

Abstract: A semiconductor device of the present invention includes, in a region 1C, a top electrode made by a semiconductor layer of an SOI substrate, a capacitive insulating film made by an insulating layer, a bottom electrode made by a supporting board, and a lead part (a high-concentration impurity region of an n type) of the bottom electrode coupled to the supporting board. An SOI transistor in a region 1B is formed over a main surface of the semiconductor layer over the insulating layer as a thin film, and threshold voltage can be adjusted by applying a voltage to a well arranged on the rear face side of the insulating layer.

公开(公告)号：US20180128974A1

公开(公告)日：2018-05-10

申请号：US15729727

申请日：2017-10-11

Applicant: Renesas Electronics Corporation

Inventor： Tetsuya IIDA ,  Yasutaka NAKASHIBA

IPC: G02B6/122 ,  G02B6/136

CPC classification number: G02B6/122 ,  G02B6/136 ,  G02B2006/12061 ,  G02B2006/12142 ,  G02F1/011 ,  H01L23/481 ,  H01L23/5226 ,  H01L27/1203

Abstract: A semiconductor device includes: a first substrate; a surface insulating film formed over an upper surface of the first substrate; a BOX layer formed over the surface insulating film; an optical waveguide made of an SOI layer formed on the BOX layer; and a first interlayer insulating film formed over the BOX layer so as to cover the optical waveguide. The semiconductor device further includes: a trench formed in the surface insulating film and the first substrate below the optical waveguide; and a cladding layer made of a buried insulating film buried in the trench. A thickness of the BOX layer is 1 μm or less, and a distance from an interface between the optical waveguide and the BOX layer to a bottom surface of the trench is 2 μm or more.

公开(公告)号：US20180102360A1

公开(公告)日：2018-04-12

申请号：US15835848

申请日：2017-12-08

Applicant: Renesas Electronics Corporation

Inventor： Yasutaka NAKASHIBA ,  Yutaka AKIYAMA

IPC: H01L27/06 ,  H01L23/522

Abstract: A semiconductor chip includes a first circuit and a second circuit having different reference potentials. A first potential which is a reference potential of the first circuit is applied to the semiconductor chip through any of plural lead terminals, and a second potential which is a reference potential of the second circuit is applied to the semiconductor chip through any of plural lead terminals. A substrate of the semiconductor chip has a structure in which a buried insulating layer and a semiconductor layer of a first conductivity type are laminated on a semiconductor substrate such as a SOI substrate. A fixed potential is applied to the semiconductor substrate through a die pad and a lead terminal for a substrate potential. The fixed potential is applied to the semiconductor chip through a different route from the reference potential of the first circuit and the reference potential of the second circuit.

公开(公告)号：US20170186689A1

公开(公告)日：2017-06-29

申请号：US15456976

申请日：2017-03-13

Applicant: Renesas Electronics Corporation

Inventor： Takatsugu NEMOTO ,  Yasutaka NAKASHIBA ,  Takasuke HASHIMOTO ,  Shinichi UCHIDA ,  Kazunori GO ,  Hiroshi OE ,  Noriko YOSHIKAWA

IPC: H01L23/522 ,  G01R33/06 ,  H01L23/528 ,  G01R31/26 ,  H01F27/28 ,  H01L49/02

CPC classification number: H01L23/5227 ,  G01R15/181 ,  G01R21/00 ,  G01R31/2607 ,  G01R33/06 ,  H01F21/00 ,  H01F27/2804 ,  H01L23/5286 ,  H01L28/10

Abstract: A sensor device includes a power line and a semiconductor device. The semiconductor device includes an inductor. The inductor is formed using an interconnect layer (to be described later using FIG. 3). The power line and the semiconductor device overlap each other when viewed from a direction perpendicular to the semiconductor device. The semiconductor device includes two inductors. The power line extends between the two inductors when viewed from a direction perpendicular to the semiconductor device.

公开(公告)号：US20170125581A1

公开(公告)日：2017-05-04

申请号：US15403539

申请日：2017-01-11

Applicant: Renesas Electronics Corporation

Inventor： Tohru KAWAI ,  Yasutaka NAKASHIBA ,  Yutaka AKIYAMA

IPC: H01L29/78 ,  H01L27/07 ,  H01L29/06 ,  H01L29/739 ,  H01L29/10 ,  H01L29/423 ,  H01L23/00 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L23/4824 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/5223 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L27/0629 ,  H01L27/0733 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7803 ,  H01L2224/05624 ,  H01L2224/0603 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48464 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: Performance of a semiconductor device is improved without increasing an area size of a semiconductor chip. For example, a source electrode of a power transistor and an upper electrode of a capacitor element have an overlapping portion. In other word, the upper electrode of the capacitor element is formed over the source electrode of the power transistor through a capacitor insulating film. That is, the power transistor and the capacitor element are arranged in a laminated manner in a thickness direction of the semiconductor chip. As a result, it becomes possible to add a capacitor element to be electrically coupled to the power transistor while suppressing an increase in planar size of the semiconductor chip.

公开(公告)号：US20150048481A1

公开(公告)日：2015-02-19

申请号：US14527293

申请日：2014-10-29

Applicant: Renesas Electronics Corporation

Inventor： Takasuke HASHIMOTO ,  Shinichi UCHIDA ,  Yasutaka NAKASHIBA ,  Takatsugu NEMOTO

IPC: H01L23/522

CPC classification number: H01L23/5225 ,  H01L23/5227 ,  H01L23/585 ,  H01L2924/0002 ,  H05K9/00 ,  H01L2924/00

Abstract: To suppress the noise caused by an inductor leaks to the outside, and also to be configured such that magnetic field intensity change reaches the inductor.An inductor surrounds an internal circuit in a planar view and also is coupled electrically to the internal circuit. The upper side of the inductor is covered by an upper shield part and the lower side of the inductor is covered by a lower shield part. The upper shield part is formed by the use of a multilayered wiring layer. The upper shield part has plural first openings. The first opening overlaps the inductor in the planar view.

Abstract translation: 为了抑制由电感器引起的噪声泄漏到外部，并且还被配置为使得磁场强度变化到达电感器。 电感器在平面视图中围绕内部电路，并且还与内部电路电连接。 电感器的上侧由上屏蔽部分覆盖，电感器的下侧由下屏蔽部分覆盖。 上部屏蔽部分通过使用多层布线层形成。 上部屏蔽部分具有多个第一开口。 第一个开口在平面视图中与电感器重叠。

公开(公告)号：US20140151904A1

公开(公告)日：2014-06-05

申请号：US14176193

申请日：2014-02-10

Applicant: Renesas Electronics Corporation

Inventor： Yasutaka NAKASHIBA

IPC: H01L23/522

CPC classification number: H01L25/0655 ,  H01F17/0013 ,  H01F38/14 ,  H01L23/48 ,  H01L23/5227 ,  H01L23/528 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/157 ,  H01L2924/19042 ,  H01L2924/19104 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: In a semiconductor device, a first semiconductor chip includes a first circuit and a first inductor, and a second semiconductor chip includes a second circuit and chip-side connecting terminals. An interconnect substrate is placed over the first semiconductor chip and the second semiconductor chip. The interconnect substrate includes a second inductor and substrate-side connecting terminals. The second inductor is located above the first inductor. The chip-side connecting terminals and the two substrate-side connecting terminals are connected through first solder balls.

Abstract translation: 在半导体器件中，第一半导体芯片包括第一电路和第一电感器，第二半导体芯片包括第二电路和芯片侧连接端子。 互连基板被放置在第一半导体芯片和第二半导体芯片上。 互连基板包括第二电感器和基板侧连接端子。 第二电感器位于第一电感器的上方。 芯片侧连接端子和两个基板侧连接端子通过第一焊球连接。

公开(公告)号：US20130130442A1

公开(公告)日：2013-05-23

申请号：US13741910

申请日：2013-01-15

Applicant: Renesas Electronics Corporation

Inventor： Yasutaka NAKASHIBA ,  Kenta OGAWA

IPC: H01L21/56

CPC classification number: H01L23/5227 ,  H01L21/56 ,  H01L23/48 ,  H01L23/49534 ,  H01L23/49537 ,  H01L23/49575 ,  H01L23/544 ,  H01L23/645 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L25/0657 ,  H01L2223/6655 ,  H01L2224/04042 ,  H01L2224/29 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/29298 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83855 ,  H01L2224/85 ,  H01L2224/92147 ,  H01L2224/92247 ,  H01L2225/06562 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01021 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/0635 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/00012 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A first semiconductor chip and a second semiconductor chip are overlapped with each other in a direction in which a first multilayer interconnect layer and a second multilayer interconnect layer are opposed to each other. When seen in a plan view, a first inductor and a second inductor are overlapped. The first semiconductor chip and the second semiconductor chip have non-opposed areas which are not opposed to each other. The first multilayer interconnect layer has a first external connection terminal in the non-opposed area, and the second multilayer interconnect layer has a second external connection terminal in the non-opposed area.

Abstract translation: 第一半导体芯片和第二半导体芯片在第一多层互连层和第二多层互连层彼此相对的方向上彼此重叠。 当在平面图中看到时，第一电感器和第二电感器重叠。 第一半导体芯片和第二半导体芯片具有不相对的非对置区域。 第一多层互连层在非对置区域中具有第一外部连接端子，并且第二多层互连层在非对置区域中具有第二外部连接端子。