公开(公告)号：US10186542B1

公开(公告)日：2019-01-22

申请号：US15652508

申请日：2017-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chao Chiu ,  Kai Tzeng ,  Chih-Chien Wang ,  Chun-Wei Chang ,  Ching-Sen Kuo ,  Feng-Jia Shiu ,  Cheng-Ta Wu

IPC: H01L27/00 ,  H01L27/146 ,  H01L21/761 ,  H01L21/027 ,  H01L21/265 ,  G03F7/09 ,  G03F7/095 ,  G03F7/11 ,  G03F7/16 ,  G03F7/20 ,  G03F7/38 ,  G03F7/32

Abstract: Various examples of a technique for forming a pattern for substrate fabrication are disclosed herein. In an example, a method includes receiving a substrate. A patterned resist is formed on the substrate and has a trench defined therein. A dielectric is deposited on the patterned resist and within the trench such that the dielectric narrows a width of the trench to further define the trench. A fabrication process is performed on a region of the substrate underlying the trench defined by the dielectric.

公开(公告)号：US09893185B2

公开(公告)日：2018-02-13

申请号：US15054133

申请日：2016-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Yu-Ting Lin ,  Po-Kai Hsiao ,  Po-Kang Ho ,  Ting-Chun Wang

IPC: H01L29/76 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/7848 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66545

Abstract: A FinFET including a substrate, a plurality of isolation structures, a plurality of blocking layers, and a gate stack is provided. The substrate has a plurality of semiconductor fins. The isolation structures are located on the substrate to isolate the semiconductor fins. In addition, the semiconductor fins protrude from the isolation structures. The blocking layers are located between the isolation structures and the semiconductor fins. The material of the blocking layers is different from the material of the isolation structures. The gate stack is disposed across portions of the semiconductor fins, portions of the blocking layers and portions of the isolation structures. In addition, a method for fabricating the FinFET is also provided.

公开(公告)号：US20170250280A1

公开(公告)日：2017-08-31

申请号：US15054086

申请日：2016-02-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ta Wu ,  Yung-Yu Wang ,  Yung-Hsiang Chan ,  Chia-Ying Tsai ,  Ting-Chun Wang

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L21/02236 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/785

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate structure, spacers and strained source and drain regions is described. The at least one gate structure is disposed over the substrate and on the isolation structures. The spacers are disposed on sidewalls of the at least one gate structure. First blocking material layers are disposed on the spacers. The strained source and drain regions are disposed at two opposite sides of the at least one gate structure. Second blocking material layers are disposed on the strained source and drain regions. The first and second blocking material layers comprise oxygen-rich oxide materials.

公开(公告)号：US09666692B2

公开(公告)日：2017-05-30

申请号：US14815547

申请日：2015-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Ta Wu ,  Ting-Chun Wang ,  Yuan-Nien Chen

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/3115 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/3115 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device includes a semiconductor fin, a first silicon nitride based layer, a lining oxide layer, a second silicon nitride based layer and a gate oxide layer. The semiconductor fin has a top surface, a first side surface adjacent to the top surface, and a second side surface which is disposed under and adjacent to the first side surface. The first silicon nitride based layer peripherally encloses the second side surface of the semiconductor fin. The lining oxide layer is disposed conformal to the first silicon nitride based layer. The second silicon nitride based layer is disposed conformal to the lining oxide layer. The gate oxide layer is disposed conformal to the top surface and the first side surface of the semiconductor fin.

公开(公告)号：US09634096B2

公开(公告)日：2017-04-25

申请号：US14755990

申请日：2015-06-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Tung-I Lin ,  Wei-Li Chen

IPC: H01L21/70 ,  H01L29/167 ,  H01L29/06 ,  H01L21/762 ,  H01L21/3065 ,  H01L21/02

CPC classification number: H01L29/167 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/3065 ,  H01L21/76224 ,  H01L21/76237 ,  H01L29/0649

Abstract: A semiconductor device includes a semiconductor substrate and a trench isolation. The trench isolation is located in the semiconductor substrate, and includes an epitaxial layer and a dielectric material. The epitaxial layer is in a trench of the semiconductor and is peripherally enclosed thereby, in which the epitaxial layer is formed by performing etch and epitaxy processes. The etch and epitaxy process includes etching out a portion of a sidewall of the trench and a portion of a bottom surface of the trench and forming the epitaxial layer conformal to the remaining portion of the sidewall and the remaining portion of the bottom surface. The dielectric material is peripherally enclosed by the epitaxial layer.

公开(公告)号：US09595589B2

公开(公告)日：2017-03-14

申请号：US14980553

申请日：2015-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  Tung-I Lin ,  Wei-Li Chen

IPC: H01L29/167 ,  H01L29/207 ,  H01L29/227 ,  H01L31/0288 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L27/146 ,  H01L29/06 ,  H01L29/16 ,  H01L29/165

CPC classification number: H01L29/42364 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/14614 ,  H01L27/14638 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/1037 ,  H01L29/105 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/4236 ,  H01L29/66636 ,  H01L29/66651 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure relates to a transistor device. In some embodiments, the transistor device has an epitaxial layer disposed over a substrate. The epitaxial layer is arranged between a source region and a drain region separated along a first direction. Isolation structures are arranged on opposite sides of the epitaxial layer along a second direction, perpendicular to the first direction. A gate dielectric layer is disposed over the epitaxial layer, and a conductive gate electrode is disposed over the gate dielectric layer. The epitaxial layer overlying the substrate improves the surface roughness of the substrate, thereby improving transistor device performance.

Abstract translation: 本公开涉及晶体管器件。 在一些实施例中，晶体管器件具有设置在衬底上的外延层。 外延层布置在沿着第一方向分离的源极区域和漏极区域之间。 绝缘结构沿垂直于第一方向的第二方向布置在外延层的相对侧上。 栅极电介质层设置在外延层上，并且导电栅电极设置在栅极介电层上。 覆盖衬底的外延层改善了衬底的表面粗糙度，从而提高了晶体管器件的性能。

公开(公告)号：US09577102B1

公开(公告)日：2017-02-21

申请号：US14865663

申请日：2015-09-25

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Ting Hsiao ,  Cheng-Ta Wu ,  Lun-Kuang Tan ,  Liang-Yu Yen ,  Ting-Chun Wang ,  Tsung-Han Wu ,  Wei-Ming You

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H01L21/3215 ,  H01L29/06

CPC classification number: H01L29/7856 ,  H01L21/3215 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41791 ,  H01L29/42376 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of forming a gate includes: forming a dummy gate; forming an inter layer dielectric (ILD) laterally adjacent to the dummy gate; doping a dopant into the dummy gate and the ILD, in which a surface dopant concentration of the dummy gate is lower than a surface dopant concentration of the ILD; removing the dummy gate to form a cavity after doping the dopant into the dummy gate and the ILD; and forming the gate in the cavity.

Abstract translation: 一种形成栅极的方法包括：形成一个虚拟栅极; 形成横向邻近所述虚拟栅极的层间电介质（ILD）; 将掺杂剂掺杂到伪栅极和ILD中，其中伪栅极的表面掺杂剂浓度低于ILD的表面掺杂剂浓度; 在将掺杂剂掺杂到虚拟栅极和ILD中之后去除伪栅极以形成空腔; 并在腔中形成门。

公开(公告)号：US09570557B2

公开(公告)日：2017-02-14

申请号：US14700067

申请日：2015-04-29

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chen Cheng Chou ,  Chung-Ren Sun ,  Chii-Ming Wu ,  Cheng-Ta Wu ,  Tzu kai Lin

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06 ,  H01L21/225 ,  H01L21/306

CPC classification number: H01L29/1054 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/76237 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: Techniques in fabricating a fin field-effect transistor (FinFET) include providing a substrate having a fin structure and forming an isolation region having a top surface with a first surface profile. A dopant species is implanted using a tilt angle to edge portions of the top surface. The edge portions are then removed using an etch process. In this respect, the isolation region is modified to have a second surface profile based on an etching rate that is greater than an etching rate used at other portions of the top surface. The second surface profile has a step height that is smaller than a step height corresponding to the first surface profile. The tilt implantation and etching process can be performed before a gate structure is formed, after the gate structure is formed but before the fin structure is recessed, or after the fin structure is recessed.

Abstract translation: 制造鳍状场效应晶体管（FinFET）的技术包括提供具有翅片结构的衬底，并形成具有第一表面轮廓的顶表面的隔离区域。 使用与顶表面的边缘部分倾斜的角度注入掺杂剂种类。 然后使用蚀刻工艺除去边缘部分。 在这方面，基于大于在顶表面的其它部分使用的蚀刻速率的蚀刻速率，将隔离区域修改为具有第二表面轮廓。 第二表面轮廓具有小于对应于第一表面轮廓的台阶高度的台阶高度。 倾斜注入和蚀刻处理可以在栅极结构形成之后，在栅极结构形成之后，但在鳍结构凹陷之前，或鳍结构凹陷之后进行。

公开(公告)号：US20150263123A1

公开(公告)日：2015-09-17

申请号：US14208905

申请日：2014-03-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Hung Cheng ,  Cheng-Ta Wu ,  Yeur-Luen Tu ,  Chia-Shiung Tsai ,  Ru-Liang Lee ,  I-Ting Li ,  Ming-Hsiang Kao

IPC: H01L29/51 ,  H01L29/788 ,  H01L21/28 ,  H01L29/423 ,  H01L27/115 ,  H01L29/66

CPC classification number: H01L29/42328 ,  G11C16/0433 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

Abstract: The present disclosure relates to an embedded flash memory cell having a common source oxide layer with a substantially flat top surface, disposed between a common source region and a common erase gate, and a method of formation. In some embodiments, the embedded flash memory cell has a semiconductor substrate with a common source region separated from a first drain region by a first channel region and separated from a second drain region by a second channel region. A high-quality common source oxide layer is formed by an in-situ steam generation (ISSG) process at a location overlying the common source region. First and second floating gate are disposed over the first and second channel regions on opposing sides of a common erase gate having a substantially flat bottom surface abutting a substantially flat top surface of the common source oxide layer.

Abstract translation: 本公开涉及一种具有公共源极氧化物层的嵌入式闪存单元，其具有基本上平坦的顶表面，设置在公共源极区域和公共擦除栅极之间以及形成方法。 在一些实施例中，嵌入式闪存单元具有半导体衬底，其具有通过第一沟道区与第一漏极区分离的公共源极区，并且通过第二沟道区与第二漏极区分离。 通过原位蒸汽发生（ISSG）工艺在覆盖共同源极区域的位置形成高质量的共源氧化物层。 第一和第二浮栅设置在公共擦除栅极的相对侧上的第一和第二沟道区域上，该公共栅极具有与公共源极氧化物层的基本上平坦的顶表面邻接的基本平坦的底表面。

公开(公告)号：US08816358B1

公开(公告)日：2014-08-26

申请号：US13934296

申请日：2013-07-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shu-Ju Tsai ,  Yeur-Luen Tu ,  Cheng-Ta Wu ,  Cheng-Yuan Tsai ,  Chia-Shiung Tsai ,  Xiaomeng Chen

IPC: H01L27/15 ,  H01L31/12 ,  H01L33/00 ,  H01L51/42 ,  H01L51/44 ,  H01L31/0232

CPC classification number: H01L51/44 ,  H01L27/307 ,  H01L51/0037 ,  H01L51/4213

Abstract: Some embodiments of the present disclosure relate to an optical sensor. The optical sensor includes a first electrode disposed over a semiconductor substrate. A photoelectrical conversion element, which includes a p-type layer and an n-type layer, is arranged over the first electrode to convert one or more photons having wavelength falling within a predetermined wavelength range into an electrical signal. A second electrode is disposed over the photoelectrical conversion element. The second electrode is transparent in the predetermined wavelength range. A color filter element, which is made up of plasmonic nanostructures, is disposed over the second electrode.

Abstract translation: 本公开的一些实施例涉及光学传感器。 光学传感器包括设置在半导体衬底上的第一电极。 包括p型层和n型层的光电转换元件布置在第一电极上方，以将具有落入预定波长范围内的波长的一个或多个光子转换成电信号。 第二电极设置在光电转换元件上。 第二电极在预定波长范围内是透明的。 由等离子体激元纳米结构构成的滤色器元件设置在第二电极上。