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公开(公告)号：US07411135B2
公开(公告)日：2008-08-12
申请号：US10711885
申请日：2004-10-12
IPC分类号： H01R12/04
CPC分类号： H01L23/544 , H01L22/24 , H01L22/32 , H01L22/34 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/48 , H01L2223/5448 , H01L2224/02166 , H01L2224/0392 , H01L2224/0401 , H01L2224/04042 , H01L2224/05181 , H01L2224/05624 , H01L2224/05666 , H01L2224/05681 , H01L2224/13099 , H01L2224/48463 , H01L2224/85399 , H01L2924/00014 , H01L2924/01013 , H01L2924/01022 , H01L2924/01033 , H01L2924/01073 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , Y10T29/49155 , Y10T29/49165 , Y10T29/49204 , Y10T29/49227 , H01L2224/45099
摘要： An integrated circuit has a wiring layer below an insulator layer. A pad comprises a conductive material that is on the insulator layer. The pad has a wirebond connection region and a probe pad region. An inspection mark is between the wirebond connection region and the probe pad region. The inspection mark comprises an opening in the insulator layer that is filled with the conductive material. In addition, a contact that is through the insulator layer is adapted to electrically connect the conductor wire in the wiring layer to the pad. The contact is formed of the same conductive material used for the pad and the inspection mark.
摘要翻译： 集成电路在绝缘体层下方具有布线层。 衬垫包括位于绝缘体层上的导电材料。 焊盘具有引线连接区域和探针焊盘区域。 导线连接区域和探针焊盘区域之间的检查标记。 检查标记包括填充有导电材料的绝缘体层中的开口。 此外，穿过绝缘体层的接触件适于将布线层中的导线电连接到焊盘。 接触由用于垫和检查标记的相同的导电材料形成。
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62.发明授权Prevention of backside cracks in semiconductor chips or wafers using backside film or backside wet etch 有权使用背面薄膜或背面湿蚀刻防止半导体芯片或晶片的背面裂缝公开(公告)号：US07405139B2
公开(公告)日：2008-07-29
申请号：US11462124
申请日：2006-08-03
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Jerome B. Lasky , Christopher D. Muzzy , Wolfgang Sauter
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Jerome B. Lasky , Christopher D. Muzzy , Wolfgang Sauter
IPC分类号： H01L21/322
CPC分类号： H01L29/34 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/10253 , H01L2924/15174 , H01L2924/15311 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A method of preventing the formation of cracks on the backside of a silicon (Si) semiconductor chip or wafer during the processing thereof. Also provided is a method for inhibiting the propagation of cracks, which have already formed in the backside of a silicon chip during the processing thereof and prior to the joining thereto of a substrate during the fabrication of an electronic package. The methods entail either treating the backside with a wet etch, or alternatively, applying a protective film layer thereon prior to forming an electronic package incorporating the chip or wafer.
摘要翻译： 一种防止在硅（Si）半导体芯片或晶片的后侧形成裂纹的方法。 还提供了一种在电子封装的制造期间，在处理之前和在与基板接合之前，已经形成在硅芯片背面的裂纹扩散的方法。 该方法需要用湿蚀刻处理背面，或者在形成包含芯片或晶片的电子封装之前，在其上施加保护膜层。
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63.发明申请PREVENTION OF BACKSIDE CRACKS IN SEMICONDUCTOR CHIPS OR WAFERS USING BACKSIDE FILM OR BACKSIDE WET ETCH 有权使用背面胶片或背面浸湿剂防止半导体芯片或波纹中的背面裂纹公开(公告)号：US20080122037A1
公开(公告)日：2008-05-29
申请号：US11462124
申请日：2006-08-03
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Jerome B. Lasky , Christopher D. Muzzy , Wolfgang Sauter
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Jerome B. Lasky , Christopher D. Muzzy , Wolfgang Sauter
CPC分类号： H01L29/34 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16225 , H01L2924/00014 , H01L2924/10253 , H01L2924/15174 , H01L2924/15311 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A method of preventing the formation of cracks on the backside of a silicon (Si) semiconductor chip or wafer during the processing thereof. Also provided is a method for inhibiting the propagation of cracks, which have already formed in the backside of a silicon chip during the processing thereof and prior to the joining thereto of a substrate during the fabrication of an electronic package. The methods entail either treating the backside with a wet etch, or alternatively, applying a protective film layer thereon prior to forming an electronic package incorporating the chip or wafer.
摘要翻译： 一种防止在硅（Si）半导体芯片或晶片的后侧形成裂纹的方法。 还提供了一种在电子封装的制造期间，在处理之前和在与基板接合之前，已经形成在硅芯片背面的裂纹扩散的方法。 该方法需要用湿蚀刻处理背面，或者在形成包含芯片或晶片的电子封装之前，在其上施加保护膜层。
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公开(公告)号：US20080099877A1
公开(公告)日：2008-05-01
申请号：US11553176
申请日：2006-10-26
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L23/5258 , H01L23/5254 , H01L23/5256 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A conductor-filled damage propagation barrier is formed extending into a low-k dielectric layer between a fuse and an adjacent circuit element for preventing propagation of damage during a fuse blow operation. Conductor material filling the damage propagation barrier is formed from the same conductor layer as that used to form an interconnect structure.
摘要翻译： 导体填充的损伤传播屏障形成为延伸到保险丝和相邻电路元件之间的低k电介质层，以防止在保险丝熔断操作期间传播损坏。 填充损伤传播屏障的导体材料由与用于形成互连结构的导体层相同的导体层形成。
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65.发明授权公开(公告)号：US09000585B2
公开(公告)日：2015-04-07
申请号：US13344628
申请日：2012-01-06
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Jeffrey S. Zimmerman
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Jeffrey S. Zimmerman
CPC分类号： H01L24/05 , H01L23/3171 , H01L23/3192 , H01L24/03 , H01L24/13 , H01L2224/0401 , H01L2224/05006 , H01L2224/05093 , H01L2224/05567 , H01L2224/05571 , H01L2224/10122 , H01L2224/10126 , H01L2224/13006 , H01L2224/13022 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1433 , H01L2224/05552
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a dielectric material formed between a design sensitive structure and a passivation layer. The design sensitive structure comprising a lower wiring layer electrically and mechanically connected to a higher wiring level by a via farm. A method and structure is also provided.
摘要翻译： 设计结构体现在用于设计，制造或测试设计的机器可读介质中。 该设计结构包括在设计敏感结构和钝化层之间形成的电介质材料。 该设计敏感结构包括通过通孔连接器电连接和机械地连接到更高布线层的下布线层。 还提供了一种方法和结构。
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公开(公告)号：US08916463B2
公开(公告)日：2014-12-23
申请号：US13604878
申请日：2012-09-06
CPC分类号： H01L23/481 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05624 , H01L2224/061 , H01L2224/45144 , H01L2224/45147 , H01L2224/48453 , H01L2224/48463 , H01L2224/48624 , H01L2224/48824 , H01L2924/00014 , H01L2924/00 , H01L2924/00015
摘要： A splash containment structure for semiconductor structures and associated methods of manufacture are provided. A method includes: forming wire bond pads in an integrated circuit chip and forming at least one passivation layer on the chip. The at least one passivation layer includes first areas having a first thickness and second areas having a second thickness. The second thickness is greater than the first thickness. The first areas having the first thickness extend over a majority of the chip. The second areas having the second thickness are adjacent the wire bond pads.
摘要翻译： 提供了一种用于半导体结构和相关制造方法的防溅结构。 一种方法包括：在集成电路芯片中形成引线接合焊盘并在芯片上形成至少一个钝化层。 所述至少一个钝化层包括具有第一厚度的第一区域和具有第二厚度的第二区域。 第二厚度大于第一厚度。 具有第一厚度的第一区域延伸超过芯片的大部分。 具有第二厚度的第二区域与引线接合焊盘相邻。
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公开(公告)号：US08710656B2
公开(公告)日：2014-04-29
申请号：US13553882
申请日：2012-07-20
申请人： Timothy H. Daubenspeck , Brian M. Erwin , Jeffrey P. Gambino , Wolfgang Sauter , George J. Scott
发明人： Timothy H. Daubenspeck , Brian M. Erwin , Jeffrey P. Gambino , Wolfgang Sauter , George J. Scott
CPC分类号： H01L23/3192 , H01L23/525 , H01L23/562 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/14 , H01L2224/02375 , H01L2224/02377 , H01L2224/0401 , H01L2224/05008 , H01L2224/05022 , H01L2224/05093 , H01L2224/05124 , H01L2224/05147 , H01L2224/05569 , H01L2224/05572 , H01L2224/0603 , H01L2224/0614 , H01L2224/1146 , H01L2224/1147 , H01L2224/13027 , H01L2224/131 , H01L2224/14104 , H01L2224/14131 , H01L2924/00014 , H01L2924/3512 , H01L2924/00012 , H01L2924/014 , H01L2224/05552
摘要： An integrated circuit (IC) chip is disclosed including a plurality of metal vertical interconnect accesses (vias) in a back end of line (BEOL) layer, a redistribution layer (RDL) on the BEOL layer, the BEOL layer having a plurality of bond pads, each bond pad connected to at least one corresponding metal via through the RDL; and a solder bump connected to each bond pad, wherein each solder bump is laterally offset from the corresponding metal via connected to the bond pad towards a center of the IC chip by an offset distance, wherein the offset distance is non-uniform across the IC chip. In one embodiment, the offset distance for each solder bump is proportionate to a distance between the center of the IC chip and the center of the corresponding solder bump pad structure for that solder bump.
摘要翻译： 公开了一种集成电路（IC）芯片，其包括在后端（BEOL）层中的多个金属垂直互连访问（通孔），BEOL层上的再分配层（RDL），BEOL层具有多个键 焊盘，每个接合焊盘通过RDL连接到至少一个对应的金属通孔; 以及连接到每个接合焊盘的焊料凸块，其中每个焊料凸块横向偏离连接到所述接合焊盘的相应金属通孔朝向所述IC芯片的中心偏移距离，其中所述偏移距离在所述IC 芯片。 在一个实施例中，每个焊料凸块的偏移距离与IC芯片的中心与该焊料凸块的相应焊料凸块焊盘结构的中心之间的距离成比例。
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公开(公告)号：US20130299989A1
公开(公告)日：2013-11-14
申请号：US13468750
申请日：2012-05-10
申请人： Charles L. Arvin , Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
发明人： Charles L. Arvin , Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter , Timothy D. Sullivan
IPC分类号： H01L23/52 , H01L21/768
CPC分类号： H01L24/11 , H01L23/49811 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/03452 , H01L2224/0346 , H01L2224/0348 , H01L2224/03912 , H01L2224/0401 , H01L2224/05026 , H01L2224/05147 , H01L2224/05571 , H01L2224/05572 , H01L2224/056 , H01L2224/11 , H01L2224/11005 , H01L2224/11452 , H01L2224/1146 , H01L2224/11472 , H01L2224/11903 , H01L2224/11906 , H01L2224/13 , H01L2224/13006 , H01L2224/13076 , H01L2224/13082 , H01L2224/13083 , H01L2224/13084 , H01L2224/131 , H01L2224/13147 , H01L2224/16238 , H01L2924/00014 , H01L2924/01029 , H01L2924/014 , H01L2924/12042 , H01L2924/00012 , H01L2224/05552 , H01L2924/00
摘要： Chip connection structures and related methods of forming such structures are disclosed. In one case, an interconnect structure is disclosed, the structure including: a pillar connecting an integrated circuit chip and a substrate, the pillar including a barrier layer, a first copper layer over the barrier layer, and a first solder layer over the first copper layer.
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公开(公告)号：US08409980B2
公开(公告)日：2013-04-02
申请号：US13347087
申请日：2012-01-10
申请人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Marie-Claude Paquet , Wolfgang Sauter , Timothy D. Sullivan
发明人： Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Marie-Claude Paquet , Wolfgang Sauter , Timothy D. Sullivan
IPC分类号： H01L21/44
CPC分类号： H01L21/56 , H01L21/563 , H01L23/49816 , H01L24/743 , H01L24/97 , H01L29/0657 , H01L2224/73203 , H01L2224/73204 , H01L2224/97 , H01L2924/14 , H01L2924/15311 , H01L2224/83 , H01L2224/81 , H01L2924/00
摘要： Underfill flow guide structures and methods of using the same are provided with a module. The method includes mounting bumps on a substrate. The method also includes forming underfill flow guide structures on the substrate by patterning wires with an overlay of hard substance. The underfill flow guide structures are integrated with the substrate and formed between adjacent bumps. The underfill flow guide structures are further formed to uniformly guide underfill along the substrate during capillary underfill processing.
摘要翻译： 底部填充流动引导结构及其使用方法具有模块。 该方法包括在基板上安装凸块。 该方法还包括通过用硬质材料的覆盖图案化线来在基底上形成底部填充流动引导结构。 底部填充流动引导结构与基板集成并形成在相邻的凸块之间。 底部填充流动引导结构进一步形成为在毛细管底部填充处理期间沿着基底均匀地引导底部填充物。
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70.发明授权Undercut-repair of barrier layer metallurgy for solder bumps and methods thereof 有权用于焊料凸块的阻挡层冶金的底切修复及其方法公开(公告)号：US08298930B2
公开(公告)日：2012-10-30
申请号：US12959697
申请日：2010-12-03
申请人： Charles L. Arvin , Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter
发明人： Charles L. Arvin , Timothy H. Daubenspeck , Jeffrey P. Gambino , Christopher D. Muzzy , Wolfgang Sauter
IPC分类号： H01L23/488
CPC分类号： H01L24/11 , H01L24/13 , H01L2224/02126 , H01L2224/0361 , H01L2224/0382 , H01L2224/03912 , H01L2224/10126 , H01L2224/1147 , H01L2224/1182 , H01L2224/11912 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2924/0001 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01072 , H01L2924/01074 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2924/00
摘要： A method of making a semiconductor structure includes patterning a barrier layer metallurgy (BLM) which forms an undercut beneath a solder material, and forming a repair material in the undercut and on the solder material. The method also includes removing the repair material from the solder material, and reflowing the solder material.
摘要翻译： 制造半导体结构的方法包括图案化在焊料材料下形成底切的阻挡层冶金（BLM），以及在底切和焊料材料上形成修复材料。 该方法还包括从焊料材料中去除修复材料，以及回流焊料。
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