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    Semiconductor device with through molding vias and method of making the same
    62.
    发明授权
    Semiconductor device with through molding vias and method of making the same 有权
    半导体器件具有通孔形成通孔及其制作方法

    公开(公告)号：US09469524B2

    公开(公告)日：2016-10-18

    申请号：US14851086

    申请日：2015-09-11

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    Inventor： Chun-wen Cheng ,  Jung-Huei Peng ,  Shang-Ying Tsai ,  Hung-Chia Tsai ,  Yi-Chuan Teng

    IPC: H01L21/302 ,  B81B7/00 ,  B81C1/00 ,  B81B7/02 ,  H01L23/00 ,  H01L21/56

    CPC classification number: B81B7/007 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0264 ,  B81B2207/07 ,  B81B2207/094 ,  B81B2207/095 ,  B81C1/00301 ,  B81C2203/0154 ,  B81C2203/0771 ,  H01L21/568 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/12105 ,  H01L2224/73267 ,  H01L2924/18162

    Abstract: A method of forming a semiconductor device includes bonding a capping wafer and a base wafer to form a wafer package. The base wafer includes a first chip package portion, a second chip package portion, and a third chip package portion. The capping wafer includes a plurality of isolation trenches. Each isolation trench of the plurality of isolation trenches is substantially aligned with a corresponding trench region of one of the first chip package portion, the second chip package portion or the third chip package portion. The method also includes removing a portion of the capping wafer to expose a first chip package portion contact, a second chip package portion contact, and a third chip package portion contact. The method further includes separating the wafer package into a first chip package configured to perform a first operation, a second chip package configured to perform a second operation, and a third chip package configured to perform a third operation.

    Abstract translation: 形成半导体器件的方法包括将封盖晶片和基底晶片接合以形成晶片封装。 基底晶片包括第一芯片封装部分，第二芯片封装部分和第三芯片封装部分。 封盖晶片包括多个隔离沟槽。 多个隔离沟槽中的每个隔离沟槽基本上与第一芯片封装部分，第二芯片封装部分或第三芯片封装部分之一的对应沟槽区域对准。 该方法还包括去除封盖晶片的一部分以暴露第一芯片封装部分触点，第二芯片封装部分触点和第三芯片封装部分触点。 该方法还包括将晶片封装分离成被配置为执行第一操作的第一芯片封装，被配置为执行第二操作的第二芯片封装以及被配置为执行第三操作的第三芯片封装。

    DEVICE WITH VERTICALLY INTEGRATED SENSORS AND METHOD OF FABRICATION
    63.
    发明申请
    DEVICE WITH VERTICALLY INTEGRATED SENSORS AND METHOD OF FABRICATION 有权
    具有垂直集成传感器的装置和制造方法

    公开(公告)号：US20160297673A1

    公开(公告)日：2016-10-13

    申请号：US14682282

    申请日：2015-04-09

    Applicant: FREESCALE SEMICONDUCTOR, INC.

    Inventor： MATTHIEU LAGOUGE ,  MAMUR CHOWDHURY

    IPC: B81B7/00 ,  B81C1/00

    CPC classification number: B81B7/0074 ,  B81B7/0006 ,  B81B7/0041 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0264 ,  B81C1/00301 ,  G01P15/0802 ,  G01P15/125

    Abstract: A device includes vertically and laterally spaced sensors that sense different physical stimuli. Fabrication of the device entails forming a device structure having a first and second wafer layers with a signal routing layer interposed between them. Active transducer elements of one or more sensors are formed in the first wafer layer and a third wafer layer is attached with the second wafer layer to produce one or more cavities in which the active transducer elements are located. A trench extends through the second wafer and through a portion of the signal routing layer. The trench electrically isolates a region of the second wafer layer surrounded by the trench from a remainder of the second wafer layer. Another active transducer element of another sensor is formed in this region. The transducer element formed in the second wafer layer may be a diaphragm for a pressure sensor of the sensor device.

    Abstract translation: 一种装置包括感测不同物理刺激的垂直和横向间隔的传感器。 装置的制造需要形成具有第一和第二晶片层的器件结构，其间插入有信号布线层。 一个或多个传感器的主动传感器元件形成在第一晶片层中，并且第三晶片层与第二晶片层连接以产生其中有源换能器元件所在的一个或多个空腔。 沟槽延伸穿过第二晶片并且穿过信号路由层的一部分。 沟槽将由沟槽围绕的第二晶片层的区域与第二晶片层的其余部分电隔离。 另一传感器的另一个有源传感器元件形成在该区域。 形成在第二晶片层中的换能器元件可以是用于传感器装置的压力传感器的隔膜。

    Micromachined 3-axis accelerometer with a single proof-mass
    64.
    发明授权
    Micromachined 3-axis accelerometer with a single proof-mass 有权
    微加工三轴加速度计，具有单个质量

    公开(公告)号：US09455354B2

    公开(公告)日：2016-09-27

    申请号：US13821853

    申请日：2011-09-18

    Applicant: Cenk Acar

    Inventor： Cenk Acar

    IPC: G01P15/18 ,  H01L29/84 ,  G01C19/5755 ,  G01P15/125 ,  G01P15/08

    CPC classification number: H01L29/84 ,  B81B7/04 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2203/051 ,  B81B2203/053 ,  B81B2203/055 ,  B81B2203/056 ,  B81B2203/058 ,  B81B2207/094 ,  G01C19/5755 ,  G01P15/125 ,  G01P15/18 ,  G01P2015/0848

    Abstract: This document discusses, among other things, an inertial measurement system including a device layer including a single proof-mass 3-axis accelerometer, a cap wafer bonded to a first surface of the device layer, and a via wafer bonded to a second surface of the device layer, wherein the cap wafer and the via wafer are configured to encapsulate the single proof-mass 3-axis accelerometer. The single proof-mass 3-axis accelerometer can be suspended about a single, central anchor, and can include separate x, y, and z-axis flexure bearings, wherein the x and y-axis flexure bearings are symmetrical about the single, central anchor and the z-axis flexure is not symmetrical about the single, central anchor.

    Abstract translation: 该文件尤其涉及一种包括装置层的惯性测量系统，该装置层包括单一的证明质量的3轴加速度计，与该装置层的第一表面结合的盖片晶片，以及接合到第二表面的通孔晶片 所述器件层，其中所述盖晶片和所述通孔晶片被配置为封装所述单个校验质量的3轴加速度计。 单个质量3轴加速度计可以悬挂在单个中心锚固件上，并且可以包括单独的x，y和z轴挠曲轴承，其中x和y轴挠曲轴承关于单个中心锚定体是对称的 锚和z轴弯曲对于单个中心锚不是对称的。

    Method of increasing MEMS enclosure pressure using outgassing material
    65.
    发明授权
    Method of increasing MEMS enclosure pressure using outgassing material 有权
    使用排气材料增加MEMS外壳压力的方法

    公开(公告)号：US09452925B2

    公开(公告)日：2016-09-27

    申请号：US14832786

    申请日：2015-08-21

    Applicant: InvenSense, Inc.

    Inventor： Cerina Zhang ,  Martin Lim ,  Jongwoo Shin ,  Joseph Seeger

    IPC: H01L23/02 ,  H01L21/54 ,  B81C1/00 ,  B81B7/02

    CPC classification number: B81C1/00301 ,  B81B7/007 ,  B81B7/02 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C1/0023 ,  B81C1/00238 ,  B81C1/00246 ,  B81C1/00269 ,  B81C2201/0104 ,  B81C2201/0132 ,  B81C2203/0145 ,  B81C2203/019 ,  B81C2203/035 ,  B81C2203/0792

    Abstract: Semiconductor manufacturing processes include providing a first substrate having a first passivation layer disposed above a patterned top-level metal layer, and further having a second passivation layer disposed over the first passivation layer; the second passivation layer has a top surface. The processes further include forming an opening in a first portion of the second passivation layer, and the opening exposes a portion of a surface of the first passivation layer. The processes further include patterning the second and first passivation layers to expose portions of the patterned top-level metal layer and bonding a second substrate and the first substrate to each other. The bonding occurs within a temperature range in which at least the exposed portion of the first passivation layer undergoes outgassing.

    Abstract translation: 半导体制造工艺包括提供第一衬底，其具有设置在图案化顶层金属层上方的第一钝化层，并且还具有设置在第一钝化层上的第二钝化层; 第二钝化层具有顶表面。 所述方法还包括在第二钝化层的第一部分中形成开口，并且开口暴露第一钝化层的表面的一部分。 所述方法还包括图案化第二钝化层和第一钝化层以暴露图案化顶层金属层的部分并将第二衬底和第一衬底彼此结合。 接合发生在至少第一钝化层的暴露部分经历脱气的温度范围内。

    Functional element, electronic apparatus, and moving object
    66.
    发明授权
    Functional element, electronic apparatus, and moving object 有权
    功能元件，电子设备和移动物体

    公开(公告)号：US09446939B2

    公开(公告)日：2016-09-20

    申请号：US14305259

    申请日：2014-06-16

    Applicant: Seiko Epson Corporation

    Inventor： Satoru Tanaka

    IPC: B81B3/00 ,  B81B7/00

    CPC classification number: B81B3/0097 ,  B81B7/0006 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0285

    Abstract: A functional element includes a first electrode section, a second electrode section, a first wiring line connected to the first electrode section, and a second wiring line connected to the second electrode section, the first wiring line is provided with at least one first intersecting section intersecting with a wiring line other than the second wiring line, the second wiring line includes at least one second intersecting section intersecting with a wiring line other than the first wiring line, and a difference between a number of the first intersecting sections and a number of the second intersecting sections satisfies a condition one of equal to and lower than 50% with respect to larger one of the number of the first intersecting sections and the number of the second intersecting sections.

    Abstract translation: 功能元件包括第一电极部分，第二电极部分，连接到第一电极部分的第一布线和连接到第二电极部分的第二布线，第一布线设置有至少一个第一相交部分 与第二布线以外的布线相交，第二布线包括与第一布线以外的布线交叉的至少一个第二交叉部，第一相交部的数量与第 第二交叉部分相对于第一交叉部分的数量和第二交叉部分的数量中的较大的一个满足等于或小于50％的条件一。

    Microelectromechanical sensor with out-of-plane sensing and process for manufacturing a microelectromechanical sensor
    68.
    发明授权
    Microelectromechanical sensor with out-of-plane sensing and process for manufacturing a microelectromechanical sensor 有权
    具有平面外感测的微机电传感器和用于制造微机电传感器的工艺

    公开(公告)号：US09383382B2

    公开(公告)日：2016-07-05

    申请号：US13779002

    申请日：2013-02-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Barbara Simoni ,  Carlo Valzasina

    IPC: G01P15/125 ,  B81C1/00 ,  G01P15/08 ,  B81B3/00

    CPC classification number: G01P15/125 ,  B81B3/0094 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/033 ,  B81B2203/04 ,  B81B2203/058 ,  B81C1/00198 ,  G01P15/0802

    Abstract: A microelectromechanical sensor that in one embodiment includes a supporting structure, having a substrate and electrode structures anchored to the substrate; and a sensing mass, movable with respect to the supporting structure so that a distance between the sensing mass and the substrate is variable. The sensing mass is provided with movable electrodes capacitively coupled to the electrode structures. Each electrode structure comprises a first fixed electrode and a second fixed electrode mutually insulated by a dielectric region and arranged in succession in a direction substantially perpendicular to a face of the substrate.

    Abstract translation: 一种微机电传感器，其在一个实施例中包括支撑结构，其具有衬底和锚定到衬底的电极结构; 以及相对于支撑结构可移动的感测质量，使得感测质量块和衬底之间的距离是可变的。 感测质量体具有与电极结构电容耦合的可动电极。 每个电极结构包括第一固定电极和第二固定电极，所述第一固定电极和第二固定电极通过电介质区域相互绝缘并且在基本上垂直于衬底的表面的方向上相继布置。

    Manufacturing methods for micro-electromechanical system device having electrical insulating structure
    69.
    发明授权
    Manufacturing methods for micro-electromechanical system device having electrical insulating structure 有权
    具有电绝缘结构的微机电系统装置的制造方法

    公开(公告)号：US09382112B2

    公开(公告)日：2016-07-05

    申请号：US14184496

    申请日：2014-02-19

    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

    Inventor： Yu Wen Hsu ,  Shih Ting Lin ,  Jen Yi Chen ,  Chao Ta Huang

    IPC: B81B3/00 ,  B81C1/00 ,  G01C19/5762

    CPC classification number: B81C1/00301 ,  B81B3/0086 ,  B81B2201/0242 ,  B81B2207/07 ,  B81C2203/0792 ,  G01C19/5762

    Abstract: A method for manufacturing a MEMS device includes the following operations. An SOI wafer including a device layer, an insulating layer and a handle layer is provided. The device layer is etched to form a recess and an annular protrusion surrounding the recess. A moving part and a spring of the MEMS device are formed on the recess by etching the device layer, the insulating layer and the handle layer. An anchor of the MEMS device is formed at the annular protrusion by etching the device layer, the insulating layer and the handle layer. The moving part and the anchor are connected to each other by the spring. The insulating layer is disposed between a first conductive portion and a second conductive portion of the moving part. The insulating layer is disposed between a first conductive portion and a second conductive portion of the anchor.

    Abstract translation: MEMS器件的制造方法包括以下操作。 提供了包括器件层，绝缘层和手柄层的SOI晶片。 蚀刻器件层以形成凹部和围绕凹部的环形突起。 通过蚀刻器件层，绝缘层和手柄层，在凹部上形成MEMS器件的移动部件和弹簧。 通过蚀刻器件层，绝缘层和手柄层，在环形突起处形成MEMS器件的锚。 活动部分和锚通过弹簧相互连接。 绝缘层设置在移动部件的第一导电部分和第二导电部分之间。 绝缘层设置在锚的第一导电部分和第二导电部分之间。

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