公开(公告)号：US20180182618A1

公开(公告)日：2018-06-28

申请号：US15388410

申请日：2016-12-22

Applicant: ASM IP Holding B.V.

Inventor： Timothee Blanquart ,  David de Roest

IPC: H01L21/02

CPC classification number: H01L21/02164 ,  H01L21/02126 ,  H01L21/02208 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02315 ,  H01L21/0234

Abstract: The invention relates to a method of providing a structure by depositing a layer on a substrate in a reactor. The method comprising: introducing a silicon halide precursor in the reactor; introducing a reactant gas comprising oxygen in the reactor; and, providing an energy source to create a plasma from the reactant gas so that the oxygen reacts with the first precursor in a layer comprising silicon dioxide.

公开(公告)号：US20180175029A1

公开(公告)日：2018-06-21

申请号：US15379632

申请日：2016-12-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Ying-Keung Leung ,  Chi On Chui

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L27/0886 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/0228 ,  H01L21/3105 ,  H01L21/32 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823468 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/66545 ,  H01L29/785

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin structure on a substrate; a first gate stack and a second gate stack formed on the fin structure; a dielectric material layer disposed on the first and second gate stacks, wherein the dielectric layer includes a first portion disposed on a sidewall of the first gate stack with a first thickness and a second portion disposed on a sidewall of the second gate stack with a second thickness greater than the first thickness; a first gate spacer disposed on the first portion of the dielectric material layer; and a second gate spacer disposed on the second portion of the dielectric material layer.

公开(公告)号：US20180171467A1

公开(公告)日：2018-06-21

申请号：US15849271

申请日：2017-12-20

Applicant: Hitachi Kokusai Electric Inc.

Inventor： Hiroki HATTA ,  Hideki HORITA

IPC: C23C14/54 ,  G01B21/08 ,  C23C16/52 ,  H01L21/02 ,  H01L21/66 ,  B05D1/00 ,  C23C16/34

CPC classification number: C23C14/542 ,  B05D1/60 ,  C23C16/345 ,  C23C16/45502 ,  C23C16/45548 ,  C23C16/52 ,  G01B21/085 ,  G06F17/50 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/0228 ,  H01L21/02334 ,  H01L22/12

Abstract: A technique capable of controlling a film thickness distribution formed on a surface of a substrate includes: forming a film on a substrate by performing a cycle a predetermined number of times, the cycle including: (a) supplying a source to the substrate accommodated in a process chamber; (b) exhausting the source from the process chamber; (c) supplying a reactant to the substrate accommodated in the process chamber; and (d) exhausting the reactant from the process chamber, wherein (a) through (d) are performed non-simultaneously, and the cycle further includes at least one of: (e) starting a next step with the source remaining in a center portion of a substrate surface after a first predetermined time elapses from a start of (b); and (f) starting a next step with the reactant remaining in the center portion of the substrate's surface after a second predetermined time elapses from a start of (d).

公开(公告)号：US20180148588A1

公开(公告)日：2018-05-31

申请号：US15364172

申请日：2016-11-29

Applicant: United Technologies Corporation

Inventor： Wayde R. Schmidt ,  Paul Sheedy

IPC: C09D11/102 ,  C09D11/03 ,  C04B35/571 ,  B41J2/01 ,  C23C4/134 ,  C23C4/131 ,  H01L21/02

CPC classification number: C09D11/102 ,  B41J2/01 ,  C04B35/5603 ,  C04B35/571 ,  C04B35/58 ,  C04B35/584 ,  C04B2235/36 ,  C04B2235/3817 ,  C04B2235/3852 ,  C04B2235/402 ,  C04B2235/404 ,  C04B2235/421 ,  C04B2235/422 ,  C04B2235/425 ,  C04B2235/428 ,  C04B2235/447 ,  C04B2235/483 ,  C04B2235/5288 ,  C09D11/03 ,  C09D11/101 ,  C09D183/14 ,  C09D183/16 ,  C23C4/131 ,  C23C4/134 ,  H01L21/02112 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02222 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/02628 ,  H01L21/02667

Abstract: A printable material in ink form for forming electronic and structural components capable of high temperature performance may include a polymeric or oligomeric ceramic precursor. The material may also include a filler material and an optional liquid carrier. The ceramic precursor materials may be silicon carbide, silicon oxycarbide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, gallium containing group 13 oligomeric compounds and mixtures thereof. The ceramic precursor may be deposited by a direct ink writing (DIW) process.

公开(公告)号：US09978634B2

公开(公告)日：2018-05-22

申请号：US14632690

申请日：2015-02-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Hsu Yen ,  Bang-Yu Huang ,  Chui-Ya Peng ,  Ching-Wen Chen

IPC: H01L21/762 ,  H01L21/02 ,  H01L29/06 ,  H01L21/3105 ,  C23C16/04 ,  C23C16/505

CPC classification number: H01L21/76224 ,  C23C16/045 ,  C23C16/505 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31053 ,  H01L21/31056 ,  H01L21/76229 ,  H01L29/0649

Abstract: A method for fabricating a shallow trench isolation includes forming a trench in a substrate, forming a bottom shallow trench isolation dielectric filling a gap of the trench, and forming a top shallow trench isolation dielectric on the bottom shallow trench isolation. The bottom shallow trench isolation dielectric has a concave center portion, and the top shallow trench isolation dielectric is deposited on the bottom shallow trench isolation by a high density plasma chemical vapor deposition process using low deposition to sputter ratio. A semiconductor structure having the shallow trench isolation is also disclosed.

公开(公告)号：US20180138036A1

公开(公告)日：2018-05-17

申请号：US15351221

申请日：2016-11-14

Applicant: Lam Research Corporation

Inventor： Chloe Baldasseroni ,  Shankar Swaminathan

IPC: H01L21/02 ,  H01L21/033 ,  H01L21/311

CPC classification number: H01L21/02164 ,  C23C16/402 ,  C23C16/45542 ,  C23C16/56 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02348 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144

Abstract: Methods and apparatuses for forming high modulus silicon oxide spacers using atomic layer deposition are provided. Methods involve depositing at high temperature, using high plasma energy, and post-treating deposited silicon oxide using ultraviolet radiation. Such silicon oxide spacers are suitable for use as masks in multiple patterning applications to prevent pitch walking.

公开(公告)号：US20180130870A1

公开(公告)日：2018-05-10

申请号：US15348580

申请日：2016-11-10

Applicant: Texas Instruments Incorporated

Inventor： ELIZABETH COSTNER STEWART ,  JEFFREY A. WEST ,  THOMAS D. BONIFIELD ,  JOSEPH ANDRE GALLEGOS ,  JAY SUNG CHUN ,  ZHIYI YU

IPC: H01L49/02 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L28/40 ,  H01L21/02211 ,  H01L21/02214 ,  H01L21/02216 ,  H01L21/02263 ,  H01L21/02274 ,  H01L21/31116

Abstract: A method of forming an integrated capacitor on a semiconductor surface on a substrate includes etching a capacitor dielectric layer including at least one silicon compound material layer on a bottom plate which is above and electrically isolated from the semiconductor surface to provide at least one defined dielectric feature having sloped dielectric sidewall portion. A dielectric layer is deposited to at least partially fill pits in the sloped dielectric sidewall portion to smooth a surface of the sloped dielectric sidewall portion. The dielectric layer is etched, and a top plate is then formed on top of the dielectric feature.

公开(公告)号：US09953859B2

公开(公告)日：2018-04-24

申请号：US15241431

申请日：2016-08-19

Applicant: SUMCO CORPORATION

Inventor： Yoshihiro Koga

IPC: H01L21/762 ,  H01L21/84 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/76251 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02694 ,  H01L21/31116 ,  H01L21/76254 ,  H01L21/76256 ,  H01L21/84

Abstract: Provided is an SOI wafer manufacturing method that allows production of an SOI wafer having a high gettering ability and a small resistance variance in a thickness direction of an active layer, at high productivity. The SOI wafer manufacturing method includes a first step of implanting light element ions to a surface of at least one of a first substrate and a second substrate to form, on the at least one of the first substrate and the second substrate, a modified layer in which the light element ions are present in solid solution, a second step of forming an oxide film on a surface of at least one of the first substrate and the second substrate, a third step of bonding the first substrate and the second substrate according to a bonding thermal processing, and a fourth step of obtaining an active layer by thinning the first substrate.

公开(公告)号：US20180090577A1

公开(公告)日：2018-03-29

申请号：US15685063

申请日：2017-08-24

Applicant: FUJITSU LIMITED

Inventor： Kozo Makiyama

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/66 ,  H01L21/02 ,  H03F3/193

CPC classification number: H01L29/408 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02241 ,  H01L21/02274 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/0277 ,  H01L21/30621 ,  H01L21/31116 ,  H01L21/31144 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49562 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41766 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787 ,  H02M1/4208 ,  H02M5/4585 ,  H03F1/3205 ,  H03F1/3241 ,  H03F1/3247 ,  H03F3/1935 ,  H03F3/195 ,  H03F3/21 ,  H03F3/245 ,  H03F2200/451

Abstract: A compound semiconductor device disclosed herein includes a substrate, an electron transit layer formed on the substrate, a compound semiconductor layer containing gallium and formed on the electron transit layer, a diffusion preventing layer containing gallium oxide and formed on the compound semiconductor layer, an insulation layer formed on the diffusion preventing layer, and a source electrode, a drain electrode, and a gate electrode formed over the electron transit layer at a distance from one another.

公开(公告)号：US09926624B2

公开(公告)日：2018-03-27

申请号：US14747001

申请日：2015-06-23

Applicant: TOKYO ELECTRON LIMITED

Inventor： Kazuki Yamada ,  Masato Morishima ,  Kenji Ouchi ,  Taiki Katou

IPC: C23C16/34 ,  H01J37/32 ,  C23C16/36 ,  C23C16/507 ,  H01L51/52

CPC classification number: C23C16/345 ,  C23C16/36 ,  C23C16/507 ,  H01J37/3211 ,  H01J37/32174 ,  H01J37/3244 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L51/5256

Abstract: There is provided a method of forming a sealing film to seal a device formed on a substrate, including: supplying a mixture gas including a silicon-containing gas and a halogen element-containing gas or a mixture gas including a silicon-containing gas and a gas containing a functional group having an electronegative property stronger than that of nitrogen, as a first mixture gas, into a processing container; generating plasma of the first mixture gas within the processing container; and forming a first sealing film to cover the device using the first mixture gas activated by the plasma.