公开(公告)号：US07061257B2

公开(公告)日：2006-06-13

申请号：US10889334

申请日：2004-07-12

Applicant: Igor Y. Khandros ,  A. Nicholas Sporck ,  Benjamin N. Eldridge

Inventor： Igor Y. Khandros ,  A. Nicholas Sporck ,  Benjamin N. Eldridge

IPC: G01R31/02

CPC classification number: H05K3/4015 ,  B23K1/0016 ,  B23K20/004 ,  B23K2101/40 ,  C25D5/08 ,  C25D5/22 ,  C25D21/02 ,  G01R1/06711 ,  G01R1/07342 ,  G01R1/07364 ,  G01R1/07378 ,  G01R31/2886 ,  H01L21/4853 ,  H01L21/4889 ,  H01L21/563 ,  H01L21/76897 ,  H01L22/20 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/45 ,  H01L24/49 ,  H01L24/72 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/16 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/45014 ,  H01L2224/45144 ,  H01L2224/49109 ,  H01L2224/73203 ,  H01L2224/81801 ,  H01L2224/85201 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01R12/52 ,  H05K1/141 ,  H05K3/20 ,  H05K3/308 ,  H05K3/326 ,  H05K3/3421 ,  H05K3/3426 ,  H05K3/368 ,  H05K3/4092 ,  H05K7/1069 ,  H05K2201/0397 ,  H05K2201/068 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10378 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10757 ,  H05K2201/10878 ,  H05K2201/10909 ,  H05K2201/10946 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/05599

Abstract: In a probe card assembly, a series of probe elements can be arrayed on a silicon space transformer. The silicon space transformer can be fabricated with an array of primary contacts in a very tight pitch, comparable to the pitch of a semiconductor device. One preferred primary contact is a resilient spring contact. Conductive elements in the space transformer are routed to second contacts at a more relaxed pitch. In one preferred embodiment, the second contacts are suitable for directly attaching a ribbon cable, which in turn can be connected to provide selective connection to each primary contact. The silicon space transformer is mounted in a fixture that provides for resilient connection to a wafer or device to be tested. This fixture can be adjusted to planarize the primary contacts with the plane of a support probe card board.

公开(公告)号：US07057295B2

公开(公告)日：2006-06-06

申请号：US10831697

申请日：2004-04-22

Applicant: Ted Ju

Inventor： Ted Ju

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K3/325 ,  H01L23/49811 ,  H01L24/72 ,  H01L2924/14 ,  H05K2201/0311 ,  H05K2201/10719 ,  H05K2201/10946

Abstract: An IC module assembly includes an IC module including a plurality of pads disposed on a bottom thereof, a plurality of resilient members respectively soldering to the pads, and a PCB having a plurality of conductive patterns arranged on a top thereof and corresponding to the resilient members respectively, whereby the IC module electrically connects the PCB by the resilient members abutting against the conductive patterns of the PCB.

Abstract translation: IC模块组件包括IC模块，其包括设置在其底部的多个焊盘，分别焊接到焊盘的多个弹性构件以及布置在其顶部上并对应于弹性构件的多个导电图案的PCB 由此IC模块通过抵靠PCB的导电图案的弹性构件将PCB连接起来。

公开(公告)号：US20060094222A1

公开(公告)日：2006-05-04

申请号：US10977157

申请日：2004-10-29

Applicant: Chee Wong ,  Chee Lee

Inventor： Chee Wong ,  Chee Lee

IPC: H01L21/44

CPC classification number: H01L23/5286 ,  H01L23/49838 ,  H01L23/562 ,  H01L23/66 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/09418 ,  H05K2201/10719 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Integrate circuit die terminal arrangements and configurations for mounting an integrate circuit die on a package substrate to reduce package transmission paths. In one embodiment, terminals for signals sensitive to trace length outside a die are arranged at the corners of the die. The die is mounted on a package substrate in an angle with respect to a package substrate to point the corners of the die at the edges of the package substrate to reduce trace length outside the die. The center of the die may or may not coincide with the center of the substrate. In one embodiment, when compare to a centered, non-rotated die mounting position, mounting a die with corners pointing at the edges of the package substrate does not cause significant differences in substrate warpage.

Abstract translation: 集成电路管芯端子布置和配置，用于将集成电路管芯安装在封装衬底上，以减少封装传输路径。 在一个实施例中，对于在管芯外部的迹线长度敏感的信号的端子设置在管芯的角部。 模具相对于封装衬底以一定角度安装在封装衬底上，以将芯片的角部指向封装衬底的边缘，以减小管芯外部的迹线长度。 管芯的中心可以与衬底的中心重合或者不一致。 在一个实施例中，当与居中的未旋转的模具安装位置相比时，安装具有指向封装基板边缘的拐角的模具不会引起基板翘曲的显着差异。

公开(公告)号：US07032311B2

公开(公告)日：2006-04-25

申请号：US10179560

申请日：2002-06-25

Applicant: Eli Razon

Inventor： Eli Razon

IPC: H01B19/00

CPC classification number: H01L24/85 ,  H01L21/4825 ,  H01L23/49811 ,  H01L24/10 ,  H01L24/13 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/43 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45565 ,  H01L2224/45611 ,  H01L2224/45616 ,  H01L2224/45639 ,  H01L2224/45644 ,  H01L2224/45655 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48455 ,  H01L2224/48472 ,  H01L2224/73204 ,  H01L2224/78302 ,  H01L2224/78313 ,  H01L2224/78318 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19042 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01R13/2407 ,  H05K3/325 ,  H05K2201/10265 ,  H05K2201/10719 ,  H01L2924/00011 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A new and improved electrical connector is provided for Ball Grid Array (BGA) devices and Direct Chip Attach (DCA) devices that solves the prior art problems of mismatch in the coefficient of thermal between a semiconductor die and its substrate, PC board or carrier. The electrical connector consists of a resilient loop of wire that is permanently wire bonded at a first and a second bond position to an electrode or contact pad of a die or an interposer. The closed loop of wire is stable in the X and Y direction and resilient in the Z direction which enables the wire bonded die or interposer to be temporarily attached to a carrier or test board for all forms of tests as well as being removable and reworkable even after being permanently soldered in place on a substrate or PC board. Since the loop shaped connectors are resilient in X, Y and Z directions, the die or interposer may be clamped onto a PC board or substrate to provide a lead free electrical connection that does not require any underfill. The loop size may be made with highly conductive and/or plated (coated) wire in sizes from about 2.5 mils diameter up to about 30 mils using wire having a diameter of about 1.0 mils up to 5.0 mils to replace prior art balls used on pads of about 3 mils size or greater.

公开(公告)号：US20060067041A1

公开(公告)日：2006-03-30

申请号：US10955676

申请日：2004-09-29

Applicant: Ashok Kabadi ,  Frank DeWeese

Inventor： Ashok Kabadi ,  Frank DeWeese

IPC: G06F1/16

CPC classification number: H05K7/1007 ,  H01R12/585 ,  H01R12/7052 ,  H01R12/7064 ,  H01R12/7076 ,  H05K3/301 ,  H05K3/308 ,  H05K3/325 ,  H05K2201/10325 ,  H05K2201/10704 ,  H05K2201/10719

Abstract: The apparatus and method described herein are for coupling an integrated circuit to a circuit board, while eliminating the need for a backing plate, when a compression socket is utilized. A plurality of tension pins are coupled to an integrated circuit for engaging a plurality of corresponding barrels in a circuit board to compress a compression socket to make an electrical connection between the integrated circuit and the circuit board.

Abstract translation: 当使用压缩插座时，本文描述的装置和方法用于将集成电路耦合到电路板，同时消除对背板的需要。 多个张紧销耦合到集成电路，用于接合电路板中的多个对应的筒以压缩压缩插座以在集成电路和电路板之间形成电连接。

公开(公告)号：US07019403B2

公开(公告)日：2006-03-28

申请号：US10652136

申请日：2003-08-29

Applicant: Katherine M. Devanie ,  Lane V. Brown ,  Michael L. Johnson

Inventor： Katherine M. Devanie ,  Lane V. Brown ,  Michael L. Johnson

IPC: H01L23/48 ,  H05K7/10

CPC classification number: H05K3/305 ,  H01L21/563 ,  H01L2224/73203 ,  H01L2924/10253 ,  H05K3/3484 ,  H05K2201/0129 ,  H05K2201/10719 ,  H05K2203/0191 ,  H05K2203/0545 ,  Y02P70/613 ,  H01L2924/00

Abstract: A self supported underfill film adhesively bonds surface mount integrated circuit packages to a printed circuit board. The printed circuit board has conductive traces and exposed conductive pads on the surface. Solder paste is printed on the conductive pads, and one or more additional solder paste deposits are printed in an area outside the conductive pads to serve as tack pads for a film adhesive. The film adhesive is strategically positioned on the printed circuit board over the tack pads and near the conductive pads, and the surface mount integrated circuit package is then placed on the board so that the conductive pads on the package align with the conductive pads on the board. The film adhesive softens when the package is soldered to the board, and the film ultimately serves as an underfill to increase the mechanical integrity of the solder joints.

Abstract translation: 自支撑的底部填充膜将表面贴装集成电路封装粘合到印刷电路板上。 印刷电路板具有导电迹线和表面上暴露的导电焊盘。 将焊膏印刷在导电焊盘上，并且一个或多个另外的焊膏沉积物印刷在导电焊盘外部的区域中，以用作胶粘剂的粘合垫。 薄膜粘合剂在印刷电路板上定位在定位焊盘上并靠近导电焊盘，然后将表面安装集成电路封装放置在板上，使得封装上的导电焊盘与板上的导电焊盘对准 。 当封装焊接到板上时，膜粘合剂软化，并且膜最终用作底部填充物以增加焊点的机械完整性。

公开(公告)号：US07005754B2

公开(公告)日：2006-02-28

申请号：US10294407

申请日：2002-11-14

Applicant: James J. Howarth

Inventor： James J. Howarth

IPC: H01L23/544

CPC classification number: H05K3/303 ,  H01L23/3128 ,  H01L23/544 ,  H01L2223/54473 ,  H01L2924/0002 ,  H05K1/0269 ,  H05K2201/09063 ,  H05K2201/10719 ,  H05K2203/0195 ,  H05K2203/166 ,  H05K2203/167 ,  Y02P70/613 ,  Y10S439/94 ,  H01L2924/00

Abstract: A method and apparatus for aligning a semiconductor device with a corresponding landing site on a carrier substrate. At least two apertures are formed in a semiconductor device, the apertures passing from a first major surface to a second, opposing major surface of the semiconductor device. Corresponding alignment features are provided on the carrier substrate at the landing site to which the semiconductor device is to be mounted. The alignment features are aligned with the corresponding apertures to effect alignment of the semiconductor device. The alignment features may include apertures corresponding in size, shape and arrangement to the semiconductor device apertures. Alignment pins may be placed through the at least two apertures to assist with alignment.

公开(公告)号：US06963143B2

公开(公告)日：2005-11-08

申请号：US10294299

申请日：2002-11-14

Applicant: James J. Howarth

Inventor： James J. Howarth

IPC: H01L23/31 ,  H01L23/544 ,  H05K1/02 ,  H05K3/30

CPC classification number: H05K3/303 ,  H01L23/3128 ,  H01L23/544 ,  H01L2223/54473 ,  H01L2924/0002 ,  H05K1/0269 ,  H05K2201/09063 ,  H05K2201/10719 ,  H05K2203/0195 ,  H05K2203/166 ,  H05K2203/167 ,  Y02P70/613 ,  Y10S439/94 ,  H01L2924/00

Abstract: A method and apparatus for aligning a semiconductor device with a corresponding landing site on a carrier substrate. At least two apertures are formed in a semiconductor device, the apertures passing from a first major surface to a second, opposing major surface of the semiconductor device. Corresponding alignment features are provided on the carrier substrate at the landing site to which the semiconductor device is to be mounted. The alignment features are aligned with the corresponding apertures to effect alignment of the semiconductor device. The alignment features may include apertures corresponding in size, shape and arrangement to the semiconductor device apertures. Alignment pins may be placed through the at least two apertures to assist with alignment.

Abstract translation: 一种用于将半导体器件与载体衬底上的对应着地点对准的方法和装置。 在半导体器件中形成至少两个孔，所述孔从半导体器件的第一主表面到第二相对的主表面。 相应的对准特征在半导体器件要被安装到的着陆位置处设置在载体基板上。 对准特征与相应的孔对准以实现半导体器件的对准。 对准特征可以包括对应于半导体器件孔径的尺寸，形状和布置的孔。 对准销可以通过至少两个孔布置以辅助对准。

公开(公告)号：US20050236719A1

公开(公告)日：2005-10-27

申请号：US10831697

申请日：2004-04-22

Applicant: Ted Ju

Inventor： Ted Ju

IPC: H01L23/48 ,  H01L23/495 ,  H01L23/498 ,  H01L23/52 ,  H01L29/40 ,  H05K3/32

CPC classification number: H05K3/325 ,  H01L23/49811 ,  H01L24/72 ,  H01L2924/14 ,  H05K2201/0311 ,  H05K2201/10719 ,  H05K2201/10946

Abstract: An IC module assembly includes an IC module including a plurality of pads disposed on a bottom thereof, a plurality of resilient members respectively soldering to the pads, and a PCB having a plurality of conductive patterns arranged on a top thereof and corresponding to the resilient members respectively, whereby the IC module electrically connects the PCB by the resilient members abutting against the conductive patterns of the PCB.

Abstract translation: IC模块组件包括IC模块，其包括设置在其底部的多个焊盘，分别焊接到焊盘的多个弹性构件以及布置在其顶部上并对应于弹性构件的多个导电图案的PCB 由此IC模块通过抵靠PCB的导电图案的弹性部件电连接PCB。

公开(公告)号：US20050236707A1

公开(公告)日：2005-10-27

申请号：US10831795

申请日：2004-04-26

Applicant: Dustin Wood ,  Kaladhar Radhakrishnan

Inventor： Dustin Wood ,  Kaladhar Radhakrishnan

IPC: H01L23/50 ,  H01L23/64 ,  H01L23/34

CPC classification number: H01L23/50 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/15311 ,  H01L2924/19106 ,  H01L2924/3011 ,  H05K1/0262 ,  H05K2201/10325 ,  H05K2201/10719

Abstract: An integrated circuit (IC) package includes a substrate and an IC die mounted on a first side of the substrate. The IC package also includes a plurality of capacitors mounted on a second side of the substrate. The second side is opposite to the first side. The IC package further includes a plurality of conductive contact pads formed on the second side of the substrate and interspersed among the capacitors. Other embodiments are described and claimed.

Abstract translation: 集成电路（IC）封装包括安装在基板的第一侧上的基板和IC芯片。 IC封装还包括安装在基板的第二侧上的多个电容器。 第二面与第一面相反。 该IC封装还包括多个导电接触焊盘，其形成在该衬底的第二侧上并散布在该电容器之间。 描述和要求保护其他实施例。