公开(公告)号：US09148075B2

公开(公告)日：2015-09-29

申请号：US14479615

申请日：2014-09-08

Applicant: STMicroelectronics International N.V.

Inventor： Sason Sourani ,  Moshe Medina

IPC: G02B26/08 ,  H02N1/00 ,  B81B7/00 ,  G02B7/182 ,  B81B3/00

CPC classification number: H02N1/006 ,  B81B3/0043 ,  B81B7/00 ,  B81B7/008 ,  B81B2201/033 ,  B81B2201/034 ,  B81B2201/042 ,  B81B2203/0109 ,  B81B2203/0181 ,  B81B2203/058 ,  G02B7/1821 ,  G02B26/0841 ,  H02N1/008

Abstract: A Micro Electro Mechanical Systems (MEMS) device includes a rotor having first rotor teeth and second rotor teeth formed in at least two layers of silicon-on-insulator (SOI) substrate. Each rotor tooth belonging to the first rotor teeth is formed in a first layer and each rotor tooth belonging of the second rotor teeth is formed in a second layer. A stator includes first stator teeth and second stator teeth formed in at least two layers of SOI substrate. Each stator tooth belonging to the first stator teeth is formed in a first layer and each stator tooth belonging to the second stator teeth is formed in a second layer.

Abstract translation: 微机电系统（MEMS）装置包括具有形成在至少两层绝缘体上硅（SOI）衬底上的第一转子齿和第二转子齿的转子。 属于第一转子齿的每个转子齿形成在第一层中，并且属于第二转子齿的每个转子齿形成在第二层中。 定子包括形成在至少两层SOI衬底中的第一定子齿和第二定子齿。 属于第一定子齿的每个定子齿形成在第一层中，并且属于第二定子齿的每个定子齿形成在第二层中。

公开(公告)号：US09142322B2

公开(公告)日：2015-09-22

申请号：US13964299

申请日：2013-08-12

Applicant: STMicroelectronics International N.V.

Inventor： Deepak Baranwal ,  Digvijay Pratap Singh ,  Kaushik Saha

IPC: G11C29/00 ,  G11C29/08 ,  G11C29/04

CPC classification number: G11C29/08 ,  G11C29/04 ,  G11C29/76 ,  G11C2029/0409

Abstract: An embodiment of a manager includes at least one input node configured to receive information regarding a region of an integrated circuit, and a determiner configured to determine, in response to the information, a likelihood that the region will cause an error. For example, the region may include a memory, and contents of the memory may be transferred to another, more reliable memory, if the likelihood that the memory will cause an error in the data that it stores equals or exceeds a likelihood threshold.

Abstract translation: 管理器的实施例包括被配置为接收关于集成电路的区域的信息的至少一个输入节点，以及被配置为响应于该信息确定该区域将导致错误的可能性的确定器。 例如，如果存储器将导致其存储的数据中的错误等于或超过似然阈值的可能性，则该区域可以包括存储器，并且存储器的内容可以被传送到另一个更可靠的存储器。

公开(公告)号：US09136733B2

公开(公告)日：2015-09-15

申请号：US13167250

申请日：2011-06-23

Applicant: Rajesh Narwal ,  Shantanu Goel

Inventor： Rajesh Narwal ,  Shantanu Goel

IPC: H02J1/00 ,  H02J3/00 ,  H02J9/06 ,  G06F1/04 ,  G06F1/26 ,  H02M1/14

CPC classification number: H02J9/061 ,  G06F1/04 ,  G06F1/26 ,  H02J2009/068 ,  H02M1/14 ,  Y10T307/696

Abstract: A system switches between application of a first supply voltage and a second supply voltage to a load. The second supply voltage is a regulated voltage that is generated from the first supply voltage, or is alternatively generated from a reference voltage, such as bandgap. When the load is supplied from the first supply voltage, the regulated voltage is also generated from the first supply voltage. At or after switching the load to the second supply voltage, the regulated voltage is generated instead from the reference voltage. The load is a clock circuit, such as an oscillator. The controlled switching of the supply voltage for the load in the manner described addresses concerns over introducing errors in the output clock signal when the clock circuit's supply voltage is changed.

Abstract translation: 系统在向负载施加第一电源电压和第二电源电压之间切换。 第二电源电压是从第一电源电压产生的调节电压，或者是替代地从参考电压（例如带隙）产生的。 当从第一电源电压提供负载时，也从第一电源电压产生调节电压。 在将负载切换到第二电源电压之后或之后，产生调节电压而不是参考电压。 负载是时钟电路，例如振荡器。 以所述方式控制负载的电源电压切换解决了当时钟电路的电源电压改变时引入输出时钟信号中的误差的问题。

公开(公告)号：US09129685B2

公开(公告)日：2015-09-08

申请号：US14266468

申请日：2014-04-30

Applicant: STMicroelectronics International N.V.

Inventor： Vikas Rana

IPC: G11C11/4193 ,  G11C11/4195 ,  G11C16/14 ,  G11C8/08 ,  G11C16/06 ,  G11C16/26

CPC classification number: G11C16/14 ,  G11C8/08 ,  G11C16/06 ,  G11C16/26

Abstract: A word-line driver includes first, second and third transistors. The first transistor includes a gate terminal driven by a first group selection signal, a first conduction terminal driven by a second sub-group selection signal and a second conduction terminal coupled to the word-line. The second transistor includes a gate terminal driven by a second group selection signal, a second conduction terminal driven by the second sub-group selection signal, and a first conduction terminal coupled to the word-line. The third transistor includes a gate terminal driven by a third the group selection signal, a first conduction terminal driven by a first sub-group selection signal, and a second conduction terminal coupled to the word-line.

Abstract translation: 字线驱动器包括第一，第二和第三晶体管。 第一晶体管包括由第一组选择信号驱动的栅极端子，由第二子组选择信号驱动的第一导通端子和耦合到字线的第二导通端子。 第二晶体管包括由第二组选择信号驱动的栅极端子，由第二子组选择信号驱动的第二导通端子和耦合到字线的第一导电端子。 第三晶体管包括由组选择信号的第三组驱动的栅极端子，由第一子组选择信号驱动的第一导通端子和耦合到字线的第二导通端子。

公开(公告)号：US20150200632A1

公开(公告)日：2015-07-16

申请号：US14153119

申请日：2014-01-13

Applicant: STMicroelectronics International N.V.

Inventor： Pijush Kanti Panja ,  Rajesh Yadav

IPC: H03F1/30 ,  H03F3/45 ,  H03K17/687

CPC classification number: H03K17/687 ,  H03F3/45183 ,  H03F3/45753 ,  H03F2200/447 ,  H03F2203/45341 ,  H03K3/3565 ,  H03K5/2481

Abstract: A first signal received at a first transistor is compared to a second signal received at a second transistor taking into account a hysteresis value to generate a comparison output. At least one of the first and second transistors has a floating bulk. A switching circuit selectively applies first and second bulk bias voltages to the floating bulk of the first or second transistor in dependence on the comparison output. A third and fourth input signals, setting the hysteresis value, are received at third and fourth transistors and compared to generate differential outputs. At least one of the third and fourth transistors has a floating bulk. A differential amplifier determines a difference between the differential outputs for application to the floating bulk of the at least one of the third and fourth transistor and further for use as one of the first and second bulk bias voltages.

Abstract translation: 将在第一晶体管处接收的第一信号与在第二晶体管处接收的第二信号进行比较，考虑滞后值以产生比较输出。 第一和第二晶体管中的至少一个具有浮动体积。 开关电路根据比较输出选择性地将第一和第二体偏置电压施加到第一或第二晶体管的浮动体。 设置滞后值的第三和第四输入信号在第三和第四晶体管处被接收，并被比较以产生差分输出。 第三和第四晶体管中的至少一个具有浮动体积。 差分放大器确定用于施加到第三和第四晶体管中的至少一个的浮动体的差分输出之间的差异，并进一步用作第一和第二体偏置电压之一。

公开(公告)号：US09077362B2

公开(公告)日：2015-07-07

申请号：US14445765

申请日：2014-07-29

Applicant: STMicroelectronics International N.V.

Inventor： Ravindranath Ramalingaiah Munnan ,  Raghu Ravindran ,  Ravi Shekhar

IPC: H03M1/10 ,  H03M1/14 ,  H03M1/66

CPC classification number: H03M1/109 ,  H03M1/144 ,  H03M1/66

Abstract: A chip with a built-in self-test (BIST) component capable of testing the linearity of an ADC is described herein. The BIST component uses hardware registers to facilitate a sliding histogram technique to save space on the chip. A subset of detected digital codes are analyzed, and DNL and INL calculations are performed by a controller to determine whether any of the digital codes in the subset exceed maximum or minimum DNL and INL thresholds. New digital codes being detected by the ADC are added to the subset as lower-value digital codes are pushed out of the subset, maintaining the same number of digital codes being analyzed as the subset moves from lower codes detected during lower voltages to higher codes detected at higher voltages. A synchronizer and pointer ensure that the subset moves through the digital codes at the same rate as the analog input ramp source.

Abstract translation: 本文描述了具有能够测试ADC的线性度的内置自测（BIST）组件的芯片。 BIST组件使用硬件寄存器来促进滑动直方图技术，以节省芯片上的空间。 分析检测到的数字代码的子集，并由控制器执行DNL和INL计算，以确定子集中的任何数字代码是否超过最大或最小DNL和INL阈值。 当ADC将低值数字代码从子集中推出时，由ADC检测到的新数字代码被添加到子集中，当子集从较低电压下检测到的较低代码移动到检测到的较高代码时，保持相同数量的数字代码被分析 在较高的电压。 同步器和指针确保子集以与模拟输入斜坡源相同的速率移动数字代码。

公开(公告)号：US20150177605A1

公开(公告)日：2015-06-25

申请号：US14413548

申请日：2013-07-17

Applicant: STMicroelectronics International N.V.

Inventor： Frederique Roffet ,  Laurent Cuisenier

IPC: G03B21/20

CPC classification number: G03B21/2053 ,  G03B17/54 ,  G03B21/14 ,  G03B21/2033 ,  G03B21/2086 ,  H04N9/3161 ,  H04N9/3194

Abstract: A projection subsystem includes a projector for projecting an image on a projection surface and a safety feature for tuning the projector when presence of a human is detected in front of the projection surface. This safety feature includes:—an apparatus for computing a depth view corresponding to at least a portion of the projection surface,—a camera for acquiring a captured image,—a computing circuit for detecting an object between the projector and the projection surface from this depth view and determining that the object is a human from the captured image, and a control circuit for tuning the projector accordingly.

Abstract translation: 投影子系统包括用于在投影表面上投影图像的投影仪和用于在投影面前面检测到人的存在时调谐投影仪的安全特征。 该安全特征包括： - 用于计算对应于投影表面的至少一部分的深度视图的装置， - 用于获取拍摄图像的摄像机， - 用于从该投影仪检测投影仪与投影表面之间的物体的计算电路 深度视图，并且从拍摄图像确定对象是人，以及用于相应地调谐投影仪的控制电路。

公开(公告)号：US20150129967A1

公开(公告)日：2015-05-14

申请号：US14231459

申请日：2014-03-31

Applicant: STMicroelectronics International N.V.

Inventor： Anand Kumar ,  Ankit Agrawal

IPC: H01L27/12 ,  H01L29/78 ,  H01L21/265 ,  H01L21/8238 ,  H01L21/762 ,  H01L21/266 ,  H01L27/092 ,  H01L21/84

CPC classification number: H01L29/7831 ,  H01L21/26513 ,  H01L21/31111 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66484 ,  H01L29/78648

Abstract: Circuit module designs that incorporate dual gate field effect transistors are implemented with fully depleted silicon-on-insulator (FD-SOI) technology. Lowering the threshold voltages of the transistors can be accomplished through dynamic secondary gate control in which a back-biasing technique is used to operate the dual gate FD-SOI transistors with enhanced switching performance. Consequently, such transistors can operate at very low core voltage supply levels, down to as low as about 0.4 V, which allows the transistors to respond quickly and to switch at higher speeds. Performance improvements are shown in circuit simulations of an inverter, an amplifier, a level shifter, and a voltage detection circuit module.

Abstract translation: 具有双栅极场效应晶体管的电路模块设计采用完全耗尽的绝缘体上硅（FD-SOI）技术实现。 降低晶体管的阈值电压可以通过动态辅助栅极控制来实现，其中使用反向偏置技术来操作具有增强的开关性能的双栅极FD-SOI晶体管。 因此，这样的晶体管可以以低至约0.4V的非常低的核心电压供应电平工作，这允许晶体管快速响应并以更高的速度切换。 在逆变器，放大器，电平转换器和电压检测电路模块的电路仿真中示出了性能改进。

公开(公告)号：US09029921B2

公开(公告)日：2015-05-12

申请号：US14158599

申请日：2014-01-17

Applicant: STMicroelectronics International N.V.

Inventor： Alexei Ankoudinov ,  Vladimir Rodov

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/74 ,  H01L27/08 ,  H01L29/861

CPC classification number: H01L29/7412 ,  H01L27/0811 ,  H01L27/0814 ,  H01L29/861

Abstract: A two terminal device which can be used for the rectification of the current. Internally it has a regenerative coupling between MOS gates of opposite type and probe regions. This regenerative coupling allows to achieve performance better than that of ideal diode.

Abstract translation: 可用于整流电流的二端装置。 在内部，它具有相反类型的MOS栅极和探针区域之间的再生耦合。 这种再生耦合可以实现比理想二极管更好的性能。

公开(公告)号：US20150127998A1

公开(公告)日：2015-05-07

申请号：US14074341

申请日：2013-11-07

Applicant: STMicroelectronics International N.V.

Inventor： Andrea Mario Veggetti ,  Abhishek Jain ,  Amit Chhabra

IPC: G11C29/48 ,  G11C7/22 ,  G06F1/08

CPC classification number: G11C29/48 ,  G06F1/08 ,  G06F11/00 ,  G11C29/24 ,  G11C29/52

Abstract: According to an embodiment described herein, a method for testing a memory includes receiving an address and a start signal at a memory, and generating a first detector pulse at a test circuit in response to the start signal. The first detector pulse has a leading edge and a trailing edge. A data transition of a bit associated with the address is detected. The bit is a functional bit. The method further includes determining whether the bit is a weak bit by determining whether the data transition occurred after the trailing edge.

Abstract translation: 根据本文描述的实施例，用于测试存储器的方法包括在存储器处接收地址和起始信号，并且响应于起始信号在测试电路产生第一检测器脉冲。 第一检测器脉冲具有前沿和后沿。 检测与地址相关联的位的数据转换。 该位是一个功能位。 该方法还包括通过确定在后沿之后是否发生数据转换来确定该位是否为弱位。