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    HIGH-SENSITIVITY NANOSCALE WIRE SENSORS
    71.
    发明申请
    HIGH-SENSITIVITY NANOSCALE WIRE SENSORS 有权
    高灵敏性纳米线传感器

    公开(公告)号：US20100152057A1

    公开(公告)日：2010-06-17

    申请号：US12312740

    申请日：2007-11-19

    申请人： Charles M. Lieber ,  Xuan Gao ,  Gengfeng Zheng

    发明人： Charles M. Lieber ,  Xuan Gao ,  Gengfeng Zheng

    IPC分类号： C40B30/04 ,  H01L29/772 ,  C40B60/12

    CPC分类号： G01N33/552 ,  B82Y15/00 ,  B82Y30/00 ,  G01N27/4146

    摘要： The present invention generally relates to nanoscale wire devices and methods for use in determining analytes suspected to be present in a sample. The invention provides a nanoscale wire that has improved sensitivity, as the carrier concentration in the wire is controlled by an external gate voltage, such that the nanoscale wire has a Debye screening length that is greater than the average cross-sectional dimension of the nanoscale wire when the nanoscale wire is exposed to a solution suspected of containing an analyte. This Debye screening length (lambda) associated with the carrier concentration (p) inside nanoscale wire is adjusted by adjusting the gate voltage applied to an FET structure, such that the carriers in the nanoscale wire are depleted.

    摘要翻译： 本发明一般涉及用于确定疑似存在于样品中的分析物的纳米级线器件和方法。 本发明提供了一种具有改进的灵敏度的纳米线，因为线中的载流子浓度由外部栅极电压控制，使得纳米级线具有大于纳米线的平均横截面尺寸的德拜屏蔽长度 当纳米线被暴露于怀疑含有分析物的溶液时。 通过调整施加到FET结构的栅极电压来调节与纳米线内的载流子浓度（p）相关联的德拜筛选长度（λ），使得纳米线中的载流子耗尽。

    Array-based architecture for molecular electronics
    73.
    发明授权
    Array-based architecture for molecular electronics 有权
    基于阵列的分子电子学架构

    公开(公告)号：US07500213B2

    公开(公告)日：2009-03-03

    申请号：US11344884

    申请日：2006-01-31

    申请人： André DeHon ,  Charles M. Lieber

    发明人： André DeHon ,  Charles M. Lieber

    IPC分类号： G06F17/50

    CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C8/10 ,  G11C13/0023 ,  G11C13/003 ,  G11C2213/75 ,  G11C2213/77 ,  G11C2213/81 ,  H01L27/28 ,  H01L27/285 ,  H01L51/0508 ,  H01L51/0595

    摘要： An architecture for nanoscale electronics is disclosed. The architecture comprises arrays of crossed nanoscale wires having selectively programmable crosspoints. Nanoscale wires of one array are shared by other arrays, thus providing signal propagation between the arrays. Nanoscale signal restoration elements are also provided, allowing an output of a first array to be used as an input to a second array. Signal restoration occurs without routing of the signal to non-nanoscale wires.

    摘要翻译： 公开了一种用于纳米尺度电子学的架构。 该架构包括具有选择性可编程交叉点的交叉纳米线的阵列。 一个阵列的纳米线由其他阵列共享，从而在阵列之间提供信号传播。 还提供了纳米尺度信号恢复元件，允许将第一阵列的输出用作第二阵列的输入。 信号恢复发生，而不将信号路由到非纳米线。

    Nanowire heterostructures
    75.
    发明申请
    Nanowire heterostructures 有权
    纳米线异质结构

    公开(公告)号：US20080191196A1

    公开(公告)日：2008-08-14

    申请号：US11807186

    申请日：2007-05-25

    申请人： Wei Lu ,  Jie Xiang ,  Yue Wu ,  Brian P. Timko ,  Hao Yan ,  Charles M. Lieber

    发明人： Wei Lu ,  Jie Xiang ,  Yue Wu ,  Brian P. Timko ,  Hao Yan ,  Charles M. Lieber

    IPC分类号： H01L29/775 ,  H01L21/285 ,  H01L29/12

    CPC分类号： B82Y10/00 ,  G11C2213/17 ,  G11C2213/18 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/1606 ,  H01L29/165

    摘要： The present invention generally relates to nanoscale heterostructures and, in some cases, to nanowire heterostructures exhibiting ballistic transport, and/or to metal-semiconductor junctions that that exhibit no or reduced Schottky barriers. One aspect of the invention provides a solid nanowire having a core and a shell, both of which are essentially undoped. For example, in one embodiment, the core may consist essentially of undoped germanium and the shell may consist essentially of undoped silicon. Carriers are injected into the nanowire, which can be ballistically transported through the nanowire. In other embodiments, however, the invention is not limited to solid nanowires, and other configurations, involving other nanoscale wires, are also contemplated within the scope of the present invention. Yet another aspect of the invention provides a junction between a metal and a nanoscale wire that exhibit no or reduced Schottky barriers. As a non-limiting example, a nanoscale wire having a core and a shell may be in physical contact with a metal electrode, such that the Schottky barrier to the core is reduced or eliminated. Still other aspects of the invention are directed to electronic devices exhibiting such properties, and techniques for methods of making or using such devices.

    摘要翻译： 本发明一般涉及纳米尺度异质结构，在某些情况下涉及显示弹道输运的纳米线异质结构，和/或涉及没有或减少的肖特基势垒的金属 - 半导体结。 本发明的一个方面提供了具有核和壳的固体纳米线，两者都基本上是未掺杂的。 例如，在一个实施例中，芯可以主要由未掺杂的锗组成，并且壳可以基本上由未掺杂的硅组成。 载体被注入纳米线，可以通过纳米线进行弹道传输。 然而，在其它实施方案中，本发明不限于固体纳米线，并且涉及其它纳米级线的其它构型也在本发明的范围内。 本发明的另一方面提供了金属和纳米尺寸线之间的连接处，其不显示或减小肖特基势垒。 作为非限制性实例，具有芯和壳的纳米线可以与金属电极物理接触，使得芯的肖特基势垒被减少或消除。 本发明的其它方面涉及具有这种性质的电子设备，以及制造或使用这些设备的方法的技术。

    Nanoscale wire-based sublithographic programmable logic arrays
    78.
    发明授权
    Nanoscale wire-based sublithographic programmable logic arrays 有权
    纳米线基亚光刻可编程逻辑阵列

    公开(公告)号：US07274208B2

    公开(公告)日：2007-09-25

    申请号：US10856115

    申请日：2004-05-28

    申请人： André DeHon ,  Michael J. Wilson ,  Charles M. Lieber

    发明人： André DeHon ,  Michael J. Wilson ,  Charles M. Lieber

    IPC分类号： G06F7/38 ,  H03K19/173

    CPC分类号： B82Y10/00 ,  G11C11/34 ,  G11C13/02 ,  G11C29/02 ,  G11C29/025 ,  G11C29/08 ,  G11C2213/81 ,  H03K19/17736 ,  H03K19/1778

    摘要： An apparatus and methods for a sublithographic programmable logic array (PLA) are disclosed. The apparatus allows combination of non-restoring, programmable junctions and fixed (non-programmable) restoration logic to implement any logic function or any finite-state machine. The methods disclosed teach how to integrate fixed, restoration logic at sublithographic scales along with programmable junctions. The methods further teach how to integrate addressing from the microscale so that the nanoscale crosspoint junctions can be programmed after fabrication.

    摘要翻译： 公开了一种用于亚光刻可编程逻辑阵列（PLA）的装置和方法。 该装置允许非恢复，可编程结和固定（不可编程）恢复逻辑的组合来实现任何逻辑功能或任何有限状态机。 所公开的方法教导了如何将固定的，恢复逻辑与亚光刻尺以及可编程的结连接在一起。 该方法进一步教导了如何从微尺度集成寻址，使得在制造之后可以对纳米级交叉点结进行编程。