公开(公告)号：US10062692B1

公开(公告)日：2018-08-28

申请号：US15443381

申请日：2017-02-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shishir K. Ray ,  Bharat V. Krishnan ,  Jinping Liu ,  Meera S. Mohan ,  Joseph K. Kassim

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/268 ,  H01L21/306 ,  H01L29/167 ,  H01L21/285 ,  H01L29/45

Abstract: Disclosed are methods of forming field effect transistor(s) (FET) and the resulting structures. Instead of forming the FET source/drain (S/D) regions during front end of the line (FEOL) processing, they are formed during middle of the line (MOL) processing through metal plug openings in an interlayer dielectric (ILD) layer. Processes used to form the S/D regions through the metal plug openings include S/D trench formation, epitaxial semiconductor material deposition, S/D dopant implantation and S/D dopant activation, followed by silicide and metal plug formation. Since the post-MOL processing thermal budget is low, the methods ensure reduced S/D dopant deactivation, reduced S/D strain reduction, and reduced S/D dopant diffusion and, thus, enable reduced S/D resistance, optimal strain engineering, and flexible junction control, respectively. Since the S/D regions are formed through the metal plug openings, the methods eliminate overlay errors that can lead to uncontacted or partially contacted S/D regions.

公开(公告)号：US10020202B2

公开(公告)日：2018-07-10

申请号：US15099641

申请日：2016-04-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Donghun Kang ,  Balaji Kannan ,  Jinping Liu

IPC: H01L21/308 ,  H01L27/092 ,  H01L21/3065 ,  H01L21/285 ,  H01L21/306

CPC classification number: H01L21/3085 ,  H01L21/28556 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/82345 ,  H01L21/823842 ,  H01L27/088 ,  H01L27/092

Abstract: A method of fabricating multi Vth devices and the resulting device are disclosed. Embodiments include forming a high-k dielectric layer over a substrate; forming a first TiN layer, a first barrier layer, a second TiN layer, a second barrier layer, and a third TiN layer consecutively over the high-k dielectric layer; forming a first masking layer over the third TiN layer in a first region; removing the third TiN layer in second and third regions, exposing the second barrier layer in the second and third regions; removing the first masking layer; removing the exposed second barrier layer; forming a second masking layer over the third TiN layer in the first region and the second TiN layer in the second region; removing the second TiN layer in the third region, exposing the first barrier layer in the third region; removing the second masking layer; and removing the exposed first barrier layer.

公开(公告)号：US10002793B1

公开(公告)日：2018-06-19

申请号：US15464591

申请日：2017-03-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  David P. Brunco ,  Jinping Liu ,  Baofu Zhu ,  Shesh Mani Pandey

IPC: H01L21/76 ,  H01L21/8234 ,  H01L21/761 ,  H01L21/225

CPC classification number: H01L21/2254 ,  H01L21/823431 ,  H01L21/823493 ,  H01L21/823821 ,  H01L21/823892

Abstract: A gap fill method for sub-fin doping includes forming semiconductor fin arrays over a semiconductor substrate, forming a first dopant source layer over a first fin array and filling intra fin gaps within the first array, and forming a second dopant source layer over a second fin array and filling intra fin gaps within the second array. The first and second dopant source layers are recessed to expose a channel region of the fins. Thereafter, an annealing step is used to drive dopants from the dopant source layers locally into sub-fin regions of the fins below the channel regions.

公开(公告)号：US09991363B1

公开(公告)日：2018-06-05

申请号：US15657594

申请日：2017-07-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou Huang ,  Jinsheng Gao ,  Haifeng Sheng ,  Jinping Liu ,  Huy Cao ,  Hui Zang

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/321

CPC classification number: H01L29/66545 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0223 ,  H01L21/02236 ,  H01L21/0228 ,  H01L21/02323 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/32105 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437

Abstract: A contact etch stop layer includes a nitride layer formed over a sacrificial gate structure and a polysilicon layer formed over the nitride layer. During subsequent processing, the polysilicon layer is adapted to oxidize and form an oxide layer. The oxidation of the polysilicon layer effectively shields the underlying nitride contact etch stop layer from oxidation, which protects the mechanical integrity of the nitride layer.

公开(公告)号：US09984933B1

公开(公告)日：2018-05-29

申请号：US15723416

申请日：2017-10-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yiheng Xu ,  Haiting Wang ,  Wei Zhao ,  Todd B. Abrams ,  Jiehui Shu ,  Jinping Liu ,  Scott Beasor

IPC: H01L21/311 ,  H01L21/8234 ,  H01L21/306 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L21/823431 ,  H01L21/28123 ,  H01L21/30625 ,  H01L21/823481 ,  H01L29/785

Abstract: A hardmask is patterned on a first material to leave hardmask elements. The first material is patterned into fins through the hardmask. A layer of silicon is formed on the hardmask elements and the fins in processing that forms the layer of silicon thicker on the hardmask elements relative to the fins. An isolation material is formed on the layer of silicon to leave the isolation material filling spaces between the fins. The isolation material and the layer of silicon are annealed to consume relatively thinner portions of the layer of silicon and leave the layer of silicon on the hardmask elements as silicon elements. A chemical mechanical polishing (CMP) is performed on the isolation material to make the isolation material planar with the silicon elements. A first etching agent removes the silicon elements on the hardmask elements, and a second chemical agent removes the hardmask elements.

公开(公告)号：US20170338226A1

公开(公告)日：2017-11-23

申请号：US15628984

申请日：2017-06-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou Huang ,  Jinping Liu ,  Huang Liu ,  Taifong Chao

IPC: H01L27/088 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/28518 ,  H01L21/31053 ,  H01L21/31155 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66803 ,  H01L29/7856

Abstract: Various embodiments include methods and integrated circuit structures. In some cases, an integrated circuit (IC) structure includes: a substrate; a set of fin structures overlying the substrate, the set of fin structures including a substrate base and a silicide layer over the substrate base; an oxide layer located between adjacent fins in the set of fin structures; and a nitride layer over the set of fin structures, wherein a height of the nitride layer is substantially uniform across the set of fin structures.

公开(公告)号：US09812543B2

公开(公告)日：2017-11-07

申请号：US15060761

申请日：2016-03-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tek Po Rinus Lee ,  Jinping Liu ,  Ruilong Xie

IPC: H01L21/266 ,  H01L29/47 ,  H01L29/40 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/285

CPC classification number: H01L29/47 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/401 ,  H01L29/78

Abstract: Methods for forming a semiconductor device having dual Schottky barrier heights using a single metal and the resulting device are provided. Embodiments include providing a substrate having an n-FET region and a p-FET region, each region including a gate between source/drain regions; applying a mask over the n-FET region; selectively amorphizing a surface of the p-FET region source/drain regions while the n-FET region is masked; removing the mask; depositing a titanium-based metal over the n-FET and p-FET region source/drain regions; and microwave annealing.

公开(公告)号：US09805982B1

公开(公告)日：2017-10-31

申请号：US15156767

申请日：2016-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Min-hwa Chi ,  Jinping Liu

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/49

CPC classification number: H01L21/823456 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823468 ,  H01L27/0886 ,  H01L29/4916 ,  H01L29/6653 ,  H01L29/66545

Abstract: A method of adjusting work-function metal thickness includes providing a structure having a substrate, the substrate including a longitudinally extending array of fins disposed thereon. Spacers are then formed on sidewalls of fins of the array. Pillars are formed between and adjacent the spacers. A gate having dummy gate material is formed over the structure, the gate extending laterally across the spacers and fins of the array. The dummy gate material and spacers are removed from the gate to form work-function (WF) metal trenches defined by the pillars and fins within the gate. The WF metal trenches have a first trench width. A thickness of the pillars is adjusted to provide a second trench width, different from the first trench width, for the WF metal trenches. A WF metal structure is disposed within the WF metal trenches.

公开(公告)号：US09761452B1

公开(公告)日：2017-09-12

申请号：US15205528

申请日：2016-07-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Daniel Jaeger ,  Garo Jacques Derderian ,  Haifeng Sheng ,  Jinping Liu

IPC: H01L21/311 ,  H01L21/033 ,  H01L27/11

CPC classification number: H01L27/1116 ,  H01L21/3086 ,  H01L27/1104 ,  H01L28/00

Abstract: Devices and methods of fabricating integrated circuit devices with reduced cell height are provided. One method includes, for instance: obtaining an intermediate semiconductor device having a substrate including a logic area and an SRAM area, a fin material layer, and a hardmask layer; depositing a mandrel over the logic area; depositing a sacrificial spacer layer; etching the sacrificial spacer layer to define a sacrificial set of vertical spacers; etching the hardmask layer; leaving a set of vertical hardmask spacers; depositing a first spacer layer; etching the first spacer layer to define a first set of vertical spacers over the logic area; depositing an SOH layer; etching an opening in the SOH layer over the SRAM area; depositing a second spacer layer; and etching the second spacer layer to define a second set of spacers over the SRAM area.

公开(公告)号：US20200335435A1

公开(公告)日：2020-10-22

申请号：US16918053

申请日：2020-07-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Xiaoqiang Zhang ,  Haizhou Yin ,  Moosung M. Chae ,  Jinping Liu ,  Hui Zang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/525

Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.