公开(公告)号：US20070057357A1

公开(公告)日：2007-03-15

申请号：US11225648

申请日：2005-09-13

申请人： Hsien-Wei Chen

发明人： Hsien-Wei Chen

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L23/544 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/49 ,  H01L2224/73257 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06593 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A System In Package (SIP) arrangement and method of connecting a plurality of flip chips and wire bond chips with reduced wiring complexity and increase flexibility. The SIP arrangement includes at least one wire bond chip and at least one flip chip.

摘要翻译： 一种系统级封装（SIP）布置方法和连接多个倒装芯片和引线键合芯片的方法，其布线复杂性降低并且增加灵活性。 SIP布置包括至少一个引线接合芯片和至少一个倒装芯片。

公开(公告)号：US20070018331A1

公开(公告)日：2007-01-25

申请号：US11188323

申请日：2005-07-25

申请人： Hsien-Wei Chen

发明人： Hsien-Wei Chen

IPC分类号： H01L23/52 ,  H01L23/48

CPC分类号： H01L23/585 ,  H01L23/562 ,  H01L24/05 ,  H01L24/45 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48666 ,  H01L2224/48684 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48766 ,  H01L2224/48784 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00

摘要： An integrated circuit chip is provided, which includes an active circuit area, a seal ring structure, and a first dummy structure. The seal ring structure is formed at least partially around the active circuit area. The first dummy structure extends from the seal ring structure into the active circuit area. Other dummy structures that are not directly joined to the seal ring structure at a given level may be provided also to further fill in spaces between active wiring. A software algorithm included in a layout tool may allow for automatically laying out such structures in accordance with predetermined layout design rules.

公开(公告)号：US20070015365A1

公开(公告)日：2007-01-18

申请号：US11181433

申请日：2005-07-14

申请人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Hsueh-Chung Chen ,  Shin-Puu Jeng ,  Jian-Hong Lin ,  Chih-Tao Lin ,  Shih-Hsun Hsu

发明人： Hsien-Wei Chen ,  Hao-Yi Tsai ,  Hsueh-Chung Chen ,  Shin-Puu Jeng ,  Jian-Hong Lin ,  Chih-Tao Lin ,  Shih-Hsun Hsu

IPC分类号： H01L21/461

CPC分类号： H01L21/3212 ,  H01L21/31053

摘要： In one embodiment, the disclosure relates to a method and apparatus for inserting dummy patterns in sparsely populated portions of a metal layer. The dummy pattern counters the effects of variations of pattern density in a semiconductor layout which can cause uneven post-polish film thickness. An algorithm according to one embodiment of the disclosure determines the size and location of the dummy patterns based on the patterns in the metal layer by first surrounding the metal structure with small dummy pattern and then filling any remaining voids with large dummy patterns.

公开(公告)号：US20060180946A1

公开(公告)日：2006-08-17

申请号：US11058392

申请日：2005-02-15

申请人： Hsien-Wei Chen

发明人： Hsien-Wei Chen

IPC分类号： H01L23/48

CPC分类号： H01L24/05 ,  H01L24/45 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05093 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48647 ,  H01L2224/48666 ,  H01L2224/48684 ,  H01L2224/48724 ,  H01L2224/48747 ,  H01L2224/48766 ,  H01L2224/48784 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00

摘要： An integrated circuit chip is provided, which includes a bond pad structure. The bond pad structure includes a bond pad, a first metal plate, and a second metal plate. The first metal plate is located under the bond pad. The first metal plate has a first outer profile area. The second metal plate is located under the first metal plate. A cumulative top view outer profile area of the first metal plate and the second metal plate is larger than the first outer profile area of the first metal plate. The second metal plate may have a second outer profile area that is substantially equal to or larger than the first outer profile area. A first vertical axis may extend through a centroid of the first metal plate, and a centroid of the second metal plate may be laterally offset relative to the first vertical axis.

摘要翻译： 提供了一种集成电路芯片，其包括接合焊盘结构。 接合焊盘结构包括接合焊盘，第一金属板和第二金属板。 第一金属板位于接合垫下方。 第一金属板具有第一外轮廓区域。 第二金属板位于第一金属板的下方。 第一金属板和第二金属板的累积顶视外形面积大于第一金属板的第一外轮廓面积。 第二金属板可以具有基本等于或大于第一外轮廓区域的第二外轮廓区域。 第一垂直轴可以延伸穿过第一金属板的质心，并且第二金属板的质心可以相对于第一垂直轴线横向偏移。

公开(公告)号：US20050236716A1

公开(公告)日：2005-10-27

申请号：US10829583

申请日：2004-04-22

申请人： Hsuch-Chung Chen ,  Yi-Lung Cheng ,  Hsien-Wei Chen ,  Shin-Puu Jeng

发明人： Hsuch-Chung Chen ,  Yi-Lung Cheng ,  Hsien-Wei Chen ,  Shin-Puu Jeng

IPC分类号： H01L23/367 ,  H01L23/48 ,  H01L23/528

CPC分类号： H01L23/5286 ,  H01L23/3677 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure and method for dissipating heat away from a semiconductor device having a plurality of power lines is provided. The semiconductor structure includes a semiconductor substrate and a plurality of interconnect structures disposed on the substrate and in contact therewith and extending through the semiconductor device, the interconnect structures for dissipating heat to the substrate. Each of the plurality of interconnect structures comprises at least one via stack.

摘要翻译： 提供了一种半导体结构和方法，用于从具有多个电源线的半导体器件散发热量。 半导体结构包括半导体衬底和布置在衬底上并与其接触并延伸穿过半导体器件的多个互连结构，用于将热量散发到衬底的互连结构。 多个互连结构中的每一个包括至少一个通孔堆叠。

公开(公告)号：US09859235B2

公开(公告)日：2018-01-02

申请号：US12619503

申请日：2009-11-16

申请人： Yu-Wen Liu ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Shin-Puu Jeng ,  Ying-Ju Chen ,  Shang-Yun Hou ,  Pei-Haw Tsao ,  Chen-Hua Yu

发明人： Yu-Wen Liu ,  Hao-Yi Tsai ,  Hsien-Wei Chen ,  Shin-Puu Jeng ,  Ying-Ju Chen ,  Shang-Yun Hou ,  Pei-Haw Tsao ,  Chen-Hua Yu

IPC分类号： H01L23/488 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L24/05 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02125 ,  H01L2224/0215 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05096 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05541 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05566 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/05042 ,  H01L2924/05442 ,  H01L2924/00014 ,  H01L2924/2064 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599

摘要： A system and method for forming an underbump metallization (UBM) is presented. A preferred embodiment includes a raised UBM which extends through a passivation layer so as to make contact with a contact pad while retaining enough of the passivation layer between the contact pad and the UBM to adequately handle the peeling and shear stress that results from CTE mismatch and subsequent thermal processing. The UBM contact is preferably formed in either an octagonal ring shape or an array of contacts.

公开(公告)号：US09806042B2

公开(公告)日：2017-10-31

申请号：US13448217

申请日：2012-04-16

申请人： Hsien-Wei Chen ,  Ying-Ju Chen ,  Tsung-Yuan Yu ,  Yu-Feng Chen ,  Tsung-Ding Wang

发明人： Hsien-Wei Chen ,  Ying-Ju Chen ,  Tsung-Yuan Yu ,  Yu-Feng Chen ,  Tsung-Ding Wang

IPC分类号： H01L33/48 ,  H01L23/00

CPC分类号： H01L24/06 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05541 ,  H01L2224/05548 ,  H01L2224/05552 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/0603 ,  H01L2224/06131 ,  H01L2224/06133 ,  H01L2224/06179 ,  H01L2224/1134 ,  H01L2224/13005 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13166 ,  H01L2224/13181 ,  H01L2224/16145 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/1306 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/207 ,  H01L2924/206

摘要： A semiconductor device includes a semiconductor die having first and second conductive pads, and a substrate having third and fourth bonding pads. A width ratio of the first conductive pad over the third bonding pad at an inner region is different from a width ratio of the second conductive pad over the fourth bonding pad at an outer region.

公开(公告)号：US09601443B2

公开(公告)日：2017-03-21

申请号：US11706940

申请日：2007-02-13

申请人： Hao-Yi Tsai ,  Shih-Hsun Hsu ,  Shih-Cheng Chang ,  Shang-Yun Hou ,  Hsien-Wei Chen ,  Chia-Lun Tsai ,  Benson Liu ,  Shin-Puu Jeng ,  Anbiarshy Wu

发明人： Hao-Yi Tsai ,  Shih-Hsun Hsu ,  Shih-Cheng Chang ,  Shang-Yun Hou ,  Hsien-Wei Chen ,  Chia-Lun Tsai ,  Benson Liu ,  Shin-Puu Jeng ,  Anbiarshy Wu

IPC分类号： H01L21/66 ,  H01L23/48 ,  H01L23/58 ,  H01L23/00

CPC分类号： H01L23/585 ,  H01L22/34 ,  H01L24/11 ,  H01L2224/0554 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A semiconductor structure includes a daisy chain adjacent to an edge of a semiconductor chip. The daisy chain includes a plurality of horizontal metal lines distributed in a plurality of metallization layers, wherein the horizontal metal lines are serially connected; a plurality of connecting pads in a same layer and electrically connecting the horizontal metal lines, wherein the connecting pads are physically separated from each other; and a plurality of vertical metal lines, each connecting one of the connecting pads to one of the horizontal metal lines, wherein one of the plurality of connecting pads is connected to one of the plurality of horizontal metal lines by only one of the plurality of vertical metal lines; and a seal ring adjacent and electrically disconnected from the daisy chain.

公开(公告)号：US09099485B2

公开(公告)日：2015-08-04

申请号：US13419126

申请日：2012-03-13

申请人： Tsung-Yuan Yu ,  Hsien-Wei Chen

发明人： Tsung-Yuan Yu ,  Hsien-Wei Chen

IPC分类号： H01L23/50 ,  H01L21/786 ,  H01L23/58 ,  H01L23/485 ,  H01L23/00

CPC分类号： H01L23/562 ,  H01L21/76877 ,  H01L22/32 ,  H01L23/3171 ,  H01L23/485 ,  H01L23/528 ,  H01L23/544 ,  H01L23/585 ,  H01L24/00 ,  H01L24/03 ,  H01L24/05 ,  H01L2223/5446 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05647 ,  H01L2224/131 ,  H01L2924/12042 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/00

摘要： Methods and apparatuses are disclosed for forming a post-passivation interconnect (PPI) guard ring over a circuit in a wafer forming a wafer level package (WLP). A circuit device comprises a guard ring and an active area. A passivation layer is formed on top of the circuit device over the guard ring and the active area, wherein the passivation layer contains a passivation contact connected to the guard ring. A first polymer layer is formed over the passivation layer. A PPI opening is formed within the first polymer layer or within the passivation layer over the passivation contact. A PPI guard ring is formed filling the PPI opening in touch with the passivation contact and extending on top of the first polymer layer or the passivation layer.

摘要翻译： 公开了用于在形成晶片级封装（WLP）的晶片中的电路上形成钝化后互连（PPI）保护环的方法和装置。 电路装置包括保护环和有源区。 在保护环和有源区上的电路器件的顶部上形成钝化层，其中钝化层包含连接到保护环的钝化接触点。 在钝化层上形成第一聚合物层。 PPI开口形成在第一聚合物层内或者在钝化层上方钝化接触。 形成PPI保护环，填充与钝化接触相接触的PPI开口并在第一聚合物层或钝化层的顶部延伸。

公开(公告)号：US09093411B2

公开(公告)日：2015-07-28

申请号：US12984669

申请日：2011-01-05

申请人： Ying-Ju Chen ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii

发明人： Ying-Ju Chen ,  Hsien-Wei Chen ,  Hao-Yi Tsai ,  Mirng-Ji Lii

IPC分类号： H01L21/66 ,  H01L23/00

CPC分类号： H01L22/34 ,  H01L22/32 ,  H01L23/50 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/5383 ,  H01L24/05 ,  H01L29/0649 ,  H01L2224/02166 ,  H01L2224/05093 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/14 ,  H01L2924/00

摘要： A pad structure in a semiconductor wafer for wafer testing is described. The pad structure includes at least two metal pads connected there-between by a plurality of conductive visa in one or more insulation layers. A plurality of contact bars in contact with the bottom-most metal pad extends substantially vertically from the bottom-most metal pad into the substrate. An isolation structure substantially surrounds the plurality of contact bars to isolate the pad structure.

摘要翻译： 描述用于晶片测试的半导体晶片中的焊盘结构。 焊盘结构包括至少两个连接在其上的金属焊盘，其间通过一个或多个绝缘层中的多个导电签证。 与最底部的金属焊盘接触的多个接触棒从最底部的金属焊盘基本垂直地延伸到衬底中。 隔离结构基本上围绕多个接触杆以隔离垫结构。