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    Germanium photodetector schottky contact for integration with CMOS and Si nanophotonics
    71.
    发明授权
    Germanium photodetector schottky contact for integration with CMOS and Si nanophotonics 有权
    锗光电探测器肖特基接触与CMOS和Si纳米光子学一体化

    公开(公告)号：US09484367B2

    公开(公告)日：2016-11-01

    申请号：US14228106

    申请日：2014-03-27

    Applicant: International Business Machines Corporation

    Inventor： Solomon Assefa ,  Jeffrey P. Gambino ,  Steven M. Shank

    IPC: H01L21/00 ,  H01L27/146 ,  H01L31/0224 ,  H01L31/103 ,  H01L31/18 ,  H01L27/144 ,  H01L35/34 ,  H01L51/50

    CPC classification number: H01L27/146 ,  H01L27/1443 ,  H01L31/022408 ,  H01L31/103 ,  H01L31/1808 ,  H01L35/34 ,  H01L51/50 ,  Y02E10/50

    Abstract: A method of forming an integrated photonic semiconductor structure having a photodetector device and a CMOS device may include depositing a dielectric stack over the photodetector device such that the dielectric stack encapsulates the photodetector. An opening is etched into the dielectric stack down to an upper surface of a region of an active area of the photodetector. A first metal layer is deposited directly onto the upper surface of the region of the active area via the opening such that the first metal layer may cover the region of the active area. Within the same mask level, a plurality of contacts including a second metal layer are located on the first metal layer and on the CMOS device. The first metal layer isolates the active area from the occurrence of metal intermixing between the second metal layer and the active area of the photodetector.

    Abstract translation: 形成具有光电检测器件和CMOS器件的集成光子半导体结构的方法可以包括在光电检测器器件上沉积电介质堆叠，使得电介质堆叠封装光电检测器。 电介质堆叠中的开口蚀刻到光电检测器的有源区域的区域的上表面。 第一金属层经由开口直接沉积在有源区域的区域的上表面上，使得第一金属层可以覆盖有源区域的区域。 在相同的掩模级内，包括第二金属层的多个触点位于第一金属层上和CMOS器件上。 第一金属层将活性区域与第二金属层和光电检测器的有源区域之间的金属混合的发生隔离。

    Fabrication of localized SOI on localized thick box using selective epitaxy on bulk semiconductor substrates for photonics device integration
    76.
    发明授权
    Fabrication of localized SOI on localized thick box using selective epitaxy on bulk semiconductor substrates for photonics device integration 有权
    使用局部半导体衬底上的选择性外延在局部厚盒上制造局域化的SOI器件用于光子器件集成

    公开(公告)号：US09105686B2

    公开(公告)日：2015-08-11

    申请号：US13667384

    申请日：2012-11-02

    Applicant: International Business Machines Corporation

    Inventor： Solomon Assefa ,  William M. Green ,  Marwan H. Khater ,  Yurri A. Vlasov

    IPC: H01L21/762

    CPC classification number: H01L21/76205 ,  H01L21/0274 ,  H01L21/76232 ,  H01L21/76281 ,  H01L21/76283

    Abstract: Photonic devices are created by laterally growing a semiconductor material (i.e., a localized semiconductor-on-insulator layer) over a localized buried oxide (BOX) created in a semiconductor by either a trench isolation process or thermal oxidation. In one embodiment, and after trench formation in a semiconductor substrate, the trench is filled with oxide to create a localized BOX. The top surface of the BOX is recessed to depth below the topmost surface of the semiconductor substrate to expose sidewall surfaces of the semiconductor substrate within each trench. A semiconductor material is then epitaxially grown from the exposed sidewall surfaces of the semiconductor substrate.

    Abstract translation: 通过在半导体中通过沟槽隔离工艺或热氧化产生的局部掩埋氧化物（BOX）横向生长半导体材料（即，局部绝缘体上半导体层）来产生光子器件。 在一个实施例中，并且在半导体衬底中形成沟槽之后，沟槽填充有氧化物以产生局部BOX。 BOX的顶表面凹进到半导体衬底的最上表面的深度以暴露在每个沟槽内的半导体衬底的侧壁表面。 然后从半导体衬底的暴露的侧壁表面外延生长半导体材料。

    Stress engineered multi-layers for integration of CMOS and Si nanophotonics
    77.
    发明授权
    Stress engineered multi-layers for integration of CMOS and Si nanophotonics 有权
    用于集成CMOS和Si纳米光子学的应力工程多层

    公开(公告)号：US09087952B2

    公开(公告)日：2015-07-21

    申请号：US14246546

    申请日：2014-04-07

    Applicant: International Business Machines Corporation

    Inventor： Solomon Assefa ,  Tymon Barwicz ,  Swetha Kamlapurkar ,  Marwan H. Khater ,  Steven M. Shank ,  Yurii A. Vlasov

    IPC: H01L27/148 ,  H01L31/113 ,  H01L27/144

    CPC classification number: H01L31/1136 ,  H01L27/1443

    Abstract: A method of forming an integrated photonic semiconductor structure having a photonic device and a CMOS device may include depositing a first silicon nitride layer having a first stress property over the photonic device, depositing an oxide layer having a stress property over the deposited first silicon nitride layer, and depositing a second silicon nitride layer having a second stress property over the oxide layer. The deposited first silicon nitride layer, the oxide layer, and the second silicon nitride layer encapsulate the photonic device.

    Abstract translation: 形成具有光子器件和CMOS器件的集成光子半导体结构的方法可以包括在光子器件上沉积具有第一应力特性的第一氮化硅层，在沉积的第一氮化硅层上沉积具有应力特性的氧化物层 并且在所述氧化物层上沉积具有第二应力特性的第二氮化硅层。 沉积的第一氮化硅层，氧化物层和第二氮化硅层封装光子器件。

    Photonics device and CMOS device having a common gate
    80.
    发明授权
    Photonics device and CMOS device having a common gate 有权
    具有公共栅极的光子器件和CMOS器件

    公开(公告)号：US08796747B2

    公开(公告)日：2014-08-05

    申请号：US13736672

    申请日：2013-01-08

    Applicant: International Business Machines Corporation

    Inventor： Solomon Assefa ,  William M. J. Green ,  Steven M. Shank ,  Yurii A. Vlasov

    IPC: H01L21/762

    CPC classification number: H01L27/0922 ,  H01L21/28255 ,  H01L21/823437 ,  H01L21/84 ,  H01L27/0617 ,  H01L27/14 ,  H01L31/18 ,  H01L31/1808 ,  Y02E10/50

    Abstract: A semiconductor chip having a photonics device and a CMOS device which includes a photonics device portion and a CMOS device portion on a semiconductor chip; a metal or polysilicon gate on the CMOS device portion, the metal or polysilicon gate having a gate extension that extends toward the photonics device portion; a germanium gate on the photonics device portion such that the germanium gate is coplanar with the metal or polysilicon gate, the germanium gate having a gate extension that extends toward the CMOS device portion, the germanium gate extension and metal or polysilicon gate extension joined together to form a common gate; spacers formed on the germanium gate and the metal or polysilicon gate; and nitride encapsulation formed on the germanium gate. A method is also disclosed pertaining to fabricating the semiconductor chip.

    Abstract translation: 一种具有光子器件和CMOS器件的半导体芯片，其包括半导体芯片上的光子器件部分和CMOS器件部分; 在CMOS器件部分上的金属或多晶硅栅极，金属或多晶硅栅极具有朝向光子器件部分延伸的栅极延伸; 在光子器件部分上的锗栅极，使得锗栅极与金属或多晶硅栅极共面，锗栅极具有朝向CMOS器件部分延伸的栅极延伸，锗栅极延伸和金属或多晶硅栅极延伸部连接到一起 形成共同门; 在锗栅极和金属或多晶硅栅极上形成的间隔物; 并且在锗栅上形成氮化物封装。 还公开了一种制造半导体芯片的方法。

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