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    System and method for providing 3D wafer assembly with known-good-dies
    74.
    发明授权
    System and method for providing 3D wafer assembly with known-good-dies 有权

    公开(公告)号：US11114408B2

    公开(公告)日：2021-09-07

    申请号：US16687498

    申请日：2019-11-18

    Applicant: Invensas Corporation

    Inventor： Hong Shen ,  Liang Wang ,  Guilian Gao

    IPC: H01L21/00 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78 ,  H01L21/683 ,  H01L25/00 ,  H01L21/768 ,  H01L21/306 ,  H01L21/304 ,  H01L21/3105

    Abstract: Systems and methods for providing 3D wafer assembly with known-good-dies are provided. An example method compiles an index of dies on a semiconductor wafer and removes the defective dies to provide a wafer with dies that are all operational. Defective dies on multiple wafers may be removed in parallel, and resulting wafers with all good dies stacked in 3D wafer assembly. In an implementation, the spaces left by removed defective dies may be filled at least in part with operational dies or with a fill material. Defective dies may be replaced either before or after wafer-to-wafer assembly to eliminate production of defective stacked devices, or the spaces may be left empty. A bottom device wafer may also have its defective dies removed or replaced, resulting in wafer-to-wafer assembly that provides 3D stacks with no defective dies.

    HD color imaging using monochromatic CMOS image sensors integrated in 3D package
    78.
    发明授权
    HD color imaging using monochromatic CMOS image sensors integrated in 3D package 有权

    公开(公告)号：US10178363B2

    公开(公告)日：2019-01-08

    申请号：US15280661

    申请日：2016-09-29

    Applicant: Invensas Corporation

    Inventor： Hong Shen ,  Liang Wang ,  Guilian Gao ,  Arkalgud R. Sitaram

    IPC: H04N9/04 ,  H04N9/43 ,  G02B27/10 ,  G06T1/20 ,  H01L27/146 ,  H01L31/0232 ,  H01L31/028 ,  H01L31/0296 ,  H01L31/0304 ,  H01L31/032 ,  H04N5/33 ,  H04N5/374 ,  H04N9/097 ,  H04N9/76

    Abstract: HD color video using monochromatic CMOS image sensors integrated in a 3D package is provided. An example 3DIC package for color video includes a beam splitter to partition received light of an image stream into multiple light outputs. Multiple monochromatic CMOS image sensors are each coupled to one of the multiple light outputs to sense a monochromatic image stream at a respective component wavelength of the received light. Each monochromatic CMOS image sensor is specially constructed, doped, controlled, and tuned to its respective wavelength of light. A parallel processing integrator or interposer chip heterogeneously combines the respective monochromatic image streams into a full-spectrum color video stream, including parallel processing of an infrared or ultraviolet stream. The parallel processing of the monochromatic image streams provides reconstruction to HD or 4K HD color video at low light levels. Parallel processing to one interposer chip also enhances speed, spatial resolution, sensitivity, low light performance, and color reconstruction.

    Interconnection Substrates for Interconnection Between Circuit Modules, and Methods of Manufacture
    79.
    发明申请
    Interconnection Substrates for Interconnection Between Circuit Modules, and Methods of Manufacture 审中-公开

    公开(公告)号：US20180337118A1

    公开(公告)日：2018-11-22

    申请号：US16017010

    申请日：2018-06-25

    Applicant: Invensas Corporation

    Inventor： Hong Shen ,  Liang Wang ,  Gabriel Z. Guevara ,  Rajesh Katkar ,  Cyprian Emeka Uzoh ,  Laura Wills Mirkarimi

    IPC: H01L23/498 ,  H01L25/00 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065

    Abstract: An interposer (110) has contact pads at the top and/or bottom surfaces for connection to circuit modules (e.g. ICs 112). The interposer includes a substrate made of multiple layers (110.i). Each layer can be a substrate (110S), possibly a ceramic substrate, with circuitry. The substrates extend vertically. Multiple interposers are fabricated in a single structure (310) made of vertical layers (310.i) corresponding to the interposers' layers. The structure is diced along horizontal planes (314) to provide the interposers. An interposer's vertical conductive lines (similar to through-substrate vias) can be formed on the substrates' surfaces before dicing and before all the substrates are attached to each other. Thus, there is no need to make through-substrate holes for the vertical conductive lines. Non-vertical features can also be formed on the substrates' surfaces before the substrates are attached to each other. Other embodiments are also provided.

    EMBEDDED GRAPHITE HEAT SPREADER FOR 3DIC
    80.
    发明申请
    EMBEDDED GRAPHITE HEAT SPREADER FOR 3DIC 审中-公开

    公开(公告)号：US20180219001A1

    公开(公告)日：2018-08-02

    申请号：US15927494

    申请日：2018-03-21

    Applicant: Invensas Corporation

    Inventor： Guilian Gao ,  Charles G. Woychik ,  Cyprian Emeka Uzoh ,  Liang Wang

    IPC: H01L25/065 ,  H01L23/367 ,  H01L25/00 ,  H01L23/00 ,  H01L23/373 ,  H01L23/36

    Abstract: A device with thermal control is presented. In some embodiments, the device includes a plurality of die positioned in a stack, each die including a chip, interconnects through a thickness of the chip, metal features of electrically conductive composition connected to the interconnects on a bottom side of the chip, and adhesive or underfill layer on the bottom side of the chip. At least one thermally conducting layer, which can be a pyrolytic graphite layer, a layer formed of carbon nanotubes, or a graphene layer, is coupled between a top side of one of the plurality of die and a bottom side of an adjoining die in the stack. A heat sink can be coupled to the thermally conducting layer.

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