公开(公告)号：US06878615B2

公开(公告)日：2005-04-12

申请号：US09863224

申请日：2001-05-24

Applicant: Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

Inventor： Ming-Hsing Tsai ,  Jing-Cheng Lin ,  Shau-Lin Shue ,  Chen-Hua Yu

IPC: H01L21/768 ,  H01L21/4763

CPC classification number: H01L21/76844 ,  H01L21/76807 ,  H01L21/76831 ,  H01L2221/1063

Abstract: A method of forming a via in a low-k dielectric material and without the attendant via poisoning problem, or a dual damascene structure formed in the same dielectric and without the same problem are disclosed. The vertical walls of the via opening are first lined with a low-k protection layer and then covered with a barrier layer in order to prevent outgassing from the low-k dielectric material when copper is deposited into the via opening. In the case of a dual damascene structure, it is sufficient that the hole opening underlying the trench opening is first lined with the low-k protection layer. The resulting via or dual damascene structure is free of poisoned metal and, therefore, more reliable.

Abstract translation: 公开了一种在低k电介质材料中形成通孔并且不伴随通过中毒问题的方法，或者形成在相同电介质中并且没有相同问题的双镶嵌结构。 通孔开口的垂直壁首先衬有低k保护层，然后被阻挡层覆盖，以便当铜沉积到通孔中时，防止从低k电介质材料脱气。 在双镶嵌结构的情况下，沟槽开口下方的开孔首先衬有低k保护层就足够了。 所得到的通孔或双镶嵌结构没有中毒金属，因此更可靠。

公开(公告)号：US06706629B1

公开(公告)日：2004-03-16

申请号：US10338120

申请日：2003-01-07

Applicant: Jing-Cheng Lin ,  Cheng-Lin Huang ,  Winston Shue ,  Mong-Song Liang

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang ,  Winston Shue ,  Mong-Song Liang

IPC: H01L2144

CPC classification number: H01L21/76834 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76888 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A new method is provided is creating metal interconnect comprising copper. A first embodiment of the invention provides for the application of a doped layer of copper. A second embodiment of the invention provides for the deposition of a silicon nitride layer as an inter-barrier film over surfaces of an opening created in a layer of dielectric followed by removing the layer of silicon nitride from the bottom of the opening followed by depositing a doped copper-alloy seed layer over surfaces of the opening followed by plating a layer of copper over the copper-alloy seed layer.

Abstract translation: 提供了一种新的方法来产生包括铜的金属互连。 本发明的第一实施例提供了铜掺杂层的应用。 本发明的第二个实施例提供了在介质层中形成的开口的表面上沉积作为隔离膜的氮化硅层，然后从开口的底部去除氮化硅层，随后沉积 在该开口的表面上的铜掺杂合金种子层，然后在铜合金种子层上镀一层铜。

公开(公告)号：US06576543B2

公开(公告)日：2003-06-10

申请号：US09933976

申请日：2001-08-20

Applicant: Jing-Cheng Lin ,  Shau-Lin Shue

Inventor： Jing-Cheng Lin ,  Shau-Lin Shue

IPC: H01L214763

CPC classification number: H01L21/76846 ,  H01L21/28562 ,  H01L21/76856

Abstract: A method is provided for selectively depositing a silicided metal diffusion barrier layer in a semiconductor structure to reduce an electrical contact resistance with respect to an underlying copper layer while maintaining a copper diffusion resistance along the semiconductor feature sidewalls including depositing a metal nitride layer over the feature under conditions according to a CVD process such that the metal nitride layer has a relatively higher deposition rate onto feature sidewalls for a period of time compared to a deposition rate over the copper underlayer; and, exposing the metal nitride layer to a silicon containing gaseous ambient under conditions such that silicon is incorporated into the metal nitride layer to form a silicided metal nitride layer having a thickness over the copper underlayer thinner by about 10 Angstroms to 60 Angstroms compared to the feature sidewall thickness.

Abstract translation: 提供了一种用于在半导体结构中选择性地沉积硅化金属扩散阻挡层的方法，以减少相对于下面的铜层的电接触电阻，同时沿着半导体特征侧壁保持铜扩散电阻，包括在特征上沉积金属氮化物层 在根据CVD工艺的条件下，使得金属氮化物层与铜底层上的沉积速率相比，在特征侧壁上具有相对较高的沉积速率一段时间; 并且将金属氮化物层暴露于含硅气态环境条件下，使得将硅掺入金属氮化物层中以形成厚度超过铜底层的硅化物金属氮化物层，其厚度比第二层薄至约10埃至60埃 特征侧壁厚度。

公开(公告)号：US10297550B2

公开(公告)日：2019-05-21

申请号：US12774558

申请日：2010-05-05

Applicant: Hsien-Pin Hu ,  Chen-Hua Yu ,  Ming-Fa Chen ,  Jing-Cheng Lin ,  Jiun Ren Lai ,  Yung-Chi Lin

Inventor： Hsien-Pin Hu ,  Chen-Hua Yu ,  Ming-Fa Chen ,  Jing-Cheng Lin ,  Jiun Ren Lai ,  Yung-Chi Lin

IPC: H01L23/538 ,  H01L23/488 ,  H01L21/56 ,  H01L21/683 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

Abstract: A device includes an interposer, which includes a substrate having a top surface. An interconnect structure is formed over the top surface of the substrate, wherein the interconnect structure includes at least one dielectric layer, and metal features in the at least one dielectric layer. A plurality of through-substrate vias (TSVs) is in the substrate and electrically coupled to the interconnect structure. A first die is over and bonded onto the interposer. A second die is bonded onto the interposer, wherein the second die is under the interconnect structure.

公开(公告)号：US09293366B2

公开(公告)日：2016-03-22

申请号：US12769251

申请日：2010-04-28

Applicant: Jing-Cheng Lin ,  Ku-Feng Yang

Inventor： Jing-Cheng Lin ,  Ku-Feng Yang

IPC: H01L29/40 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76898 ,  H01L23/49827 ,  H01L23/5226 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13025 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2224/05552

Abstract: A device includes a substrate, and a plurality of dielectric layers over the substrate. A plurality of metallization layers is formed in the plurality of dielectric layers, wherein at least one of the plurality of metallization layers comprises a metal pad. A through-substrate via (TSV) extends from the top level of the plurality of the dielectric layers to a bottom surface of the substrate. A deep conductive via extends from the top level of the plurality of dielectric layers to land on the metal pad. A metal line is formed over the top level of the plurality of dielectric layers and interconnecting the TSV and the deep conductive via.

Abstract translation: 一种器件包括衬底和在衬底上的多个电介质层。 多个金属化层形成在多个电介质层中，其中多个金属化层中的至少一个包括金属焊盘。 贯穿衬底通孔（TSV）从多个电介质层的顶层延伸到衬底的底表面。 深导电通孔从多个电介质层的顶层延伸到金属焊盘上。 金属线形成在多个电介质层的顶层上并且互连TSV和深导电通孔。

公开(公告)号：US09153462B2

公开(公告)日：2015-10-06

申请号：US12964097

申请日：2010-12-09

Applicant: Yu-Liang Lin ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou

Inventor： Yu-Liang Lin ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou

IPC: H01L21/687 ,  H01L21/67

CPC classification number: H01L21/67051 ,  H01L21/68728

Abstract: A device and system for thin wafer cleaning is disclosed. A preferred embodiment comprises a spin chuck having at least three holding clamps. A thin wafer with a wafer frame is mounted on the spin chuck through a tape layer. When the holding clamps are unlocked, there is no interference with the removal and placement of the wafer frame. On the other hand, when the holding clamps are locked, the holding clamps are brought into contact with the outer edge of the wafer frame so as to prevent the wafer frame from moving laterally. Furthermore, the shape of the holding clamps in a locked position is capable of preventing the wafer frame from moving vertically.

Abstract translation: 公开了用于薄晶片清洁的装置和系统。 优选实施例包括具有至少三个保持夹具的旋转卡盘。 具有晶片框架的薄晶片通过带层安装在旋转卡盘上。 当保持夹具解锁时，不会干扰晶片框架的移除和放置。 另一方面，当保持夹具被锁定时，保持夹具与晶片框架的外边缘接触，以防止晶片框架横向移动。 此外，保持夹具处于锁定位置的形状能够防止晶片框架垂直移动。

公开(公告)号：US08936966B2

公开(公告)日：2015-01-20

申请号：US13369083

申请日：2012-02-08

Applicant: Jui-Pin Hung ,  Jing-Cheng Lin

Inventor： Jui-Pin Hung ,  Jing-Cheng Lin

IPC: H01L21/00

CPC classification number: H01L24/97 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/563 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/3185 ,  H01L24/11 ,  H01L24/19 ,  H01L24/94 ,  H01L24/96 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/73259 ,  H01L2224/92224 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/83

Abstract: Methods of packaging semiconductor devices are disclosed. In one embodiment, a packaging method for semiconductor devices includes providing a workpiece including a plurality of first dies, and coupling a plurality of second dies to the plurality of first dies. The plurality of second dies and the plurality of first dies are partially packaged and separated. Top surfaces of the second dies are coupled to a carrier, and the partially packaged plurality of second dies and plurality of first dies are fully packaged. The carrier is removed, and the fully packaged plurality of second dies and plurality of first dies are separated.

Abstract translation: 公开了封装半导体器件的方法。 在一个实施例中，用于半导体器件的封装方法包括提供包括多个第一裸片的工件，以及将多个第二裸片耦合到多个第一裸片。 多个第二模具和多个第一模具被部分地包装和分离。 第二管芯的顶表面耦合到载体，并且部分封装的多个第二管芯和多个第一管芯被完全封装。 移除载体，分离完全封装的多个第二模具和多个第一模具。

公开(公告)号：US08896136B2

公开(公告)日：2014-11-25

申请号：US12827563

申请日：2010-06-30

Applicant: Chen-Yu Tsai ,  Shih-Hui Wang ,  Chien-Ming Chiu ,  Chia-Ho Chen ,  Fang Wen Tsai ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Chen-Yu Tsai ,  Shih-Hui Wang ,  Chien-Ming Chiu ,  Chia-Ho Chen ,  Fang Wen Tsai ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L23/544 ,  H01L29/40 ,  H01L23/48 ,  H01L23/52 ,  H01L21/76 ,  H01L21/00 ,  H01L21/4763 ,  H01L21/44 ,  H01L21/683

CPC classification number: H01L23/481 ,  H01L21/30604 ,  H01L21/6835 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2224/13

Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.

Abstract translation: 根据实施例，结构包括具有第一区域和第二区域的基板; 穿过基板的第一区域的贯穿基板通孔（TSV）; 在所述衬底的所述第二区域上方的隔离层，所述隔离层具有凹部; 以及在所述隔离层的所述凹部中的导电材料，所述隔离层设置在所述凹部中的所述导电材料和所述基板之间。

公开(公告)号：US08846499B2

公开(公告)日：2014-09-30

申请号：US12858211

申请日：2010-08-17

Applicant: Ying-Ching Shih ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Ying-Ching Shih ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L21/30

CPC classification number: G07F17/3213 ,  B32B17/10 ,  B32B37/1207 ,  B32B37/182 ,  B32B37/185 ,  B32B2457/14 ,  H01L21/6835 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: A composite carrier structure for manufacturing semiconductor devices is provided. The composite carrier structure utilizes multiple carrier substrates, e.g., glass or silicon substrates, coupled together by interposed adhesive layers. The composite carrier structure may be attached to a wafer or a die for, e.g., backside processing, such as thinning processes. In an embodiment, the composite carrier structure comprises a first carrier substrate having through-substrate vias formed therethrough. The first substrate is attached to a second substrate using an adhesive such that the adhesive may extend into the through-substrate vias.

Abstract translation: 提供了一种用于制造半导体器件的复合载体结构。 复合载体结构利用多个载体衬底，例如玻璃或硅衬底，通过插入的粘合剂层耦合在一起。 复合载体结构可以附接到晶片或模具，用于例如背面处理，例如变薄处理。 在一个实施例中，复合载体结构包括具有贯穿其中形成的贯通基板通孔的第一载体基板。 使用粘合剂将第一衬底附接到第二衬底，使得粘合剂可以延伸到贯穿衬底通孔中。

公开(公告)号：US08829676B2

公开(公告)日：2014-09-09

申请号：US13170973

申请日：2011-06-28

Applicant: Chen-Hua Yu ,  Jing-Cheng Lin ,  Nai-Wei Liu ,  Jui-Pin Hung ,  Shin-Puu Jeng

Inventor： Chen-Hua Yu ,  Jing-Cheng Lin ,  Nai-Wei Liu ,  Jui-Pin Hung ,  Shin-Puu Jeng

IPC: H01L23/485

CPC classification number: H01L21/4853 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05008 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/73267 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2224/19 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/05552 ,  H01L2924/00 ,  H01L2224/214

Abstract: A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over the passivation layer. A package material formed of a molding compound or a polymer is over the dielectric layer. The dielectric layer includes a bottom portion between the passivation layer and the package material, and a sidewall portion between a sidewall of the metal pillar and a sidewall of the package material. A polymer layer is over the package material, the molding compound, and the metal pillar. A post-passivation interconnect (PPI) extends into the polymer layer. A solder ball is over the PPI, and is electrically coupled to the metal pad through the PPI.

Abstract translation: 封装包括具有基板的器件裸片。 模塑料与基材的侧壁接触。 金属焊盘在基板上。 钝化层具有覆盖金属焊盘的边缘部分的部分。 金属支柱已经过去并与金属垫接触。 介电层位于钝化层的上方。 由模塑料或聚合物形成的包装材料在电介质层的上面。 电介质层包括位于钝化层和封装材料之间的底部，以及在金属柱的侧壁和封装材料的侧壁之间的侧壁部分。 聚合物层在包装材料，模塑料和金属支柱之上。 后钝化互连（PPI）延伸到聚合物层中。 焊球在PPI上方，并通过PPI电耦合到金属焊盘。