公开(公告)号：US06593548B2

公开(公告)日：2003-07-15

申请号：US10130207

申请日：2002-05-14

申请人： Hideki Matsumura ,  Atsushi Masuda ,  Keiji Ishibashi ,  Masahiko Tanaka ,  Minoru Karasawa

发明人： Hideki Matsumura ,  Atsushi Masuda ,  Keiji Ishibashi ,  Masahiko Tanaka ,  Minoru Karasawa

IPC分类号： F27B514

CPC分类号： C23C16/45519 ,  C23C16/24 ,  C23C16/345 ,  C23C16/44 ,  C23C16/452

摘要： A heating element CVD device capable of providing a high productivity and decomposing and/or activating the material gas led into a processing container by a heating element and stacking film on a substrate disposed in the processing container, wherein the connection part area of the heating element to a connection terminal for connecting the hearing element to a power supply mechanism is not exposed to a space inside the processing container, specifically, the connection part area is covered by a cylindrical body or a platy body covering the connection part area while providing a space part thereof from the hearing element, or the connection part area allows the space part to be present in a space thereof from the connection terminal and is covered by the cylindrical body or platy body covering the connection part area while providing the space part in a space thereof from the heating element, and hydrogen gas is led from the connection terminal side into the processing container through the space part, whereby the portion of the heating element near the connection part to the power supply mechanism can be prevented from being deteriorated by the material gas, the material gas can be prevented from reacting with cleaning gas during the cleaning for removing the film adhered to the inside of the processing container, the service life of the heating element can be increased, and a film forming environment can be stabilized.

摘要翻译： 一种加热元件CVD装置，其能够提供高生产率并且分解和/或激活通过加热元件引导到处理容器中的材料气体，并且在设置在处理容器中的基板上堆叠膜，其中加热元件的连接部分区域 将用于将听力元件连接到电源机构的连接端子不暴露于处理容器内部的空间，具体地，连接部分区域被覆盖在连接部分区域上的圆柱体或板状体覆盖，同时提供空间 或者连接部分区域可以使空间部分从连接端子出现在其空间中，并且被覆盖在连接部分区域上的圆柱体或板状体覆盖，同时在空间中提供空间部分 来自加热元件，并且氢气从连接端子侧被引导到处理容器中 由于空间部分，由此可以防止靠近供电机构的连接部分附近的加热元件的部分被材料气体劣化，因此可以防止材料气体在清洁期间与清洁气体反应以除去膜 附着在加工容器的内部，能够提高加热元件的使用寿命，能够使成膜环境稳定。

公开(公告)号：US06375756B1

公开(公告)日：2002-04-23

申请号：US09633013

申请日：2000-08-04

申请人： Keiji Ishibashi

发明人： Keiji Ishibashi

IPC分类号： B08B700

CPC分类号： C23C16/4405 ,  Y10S438/905

摘要： A method for efficiently and completely removing a film deposited inside a film forming chamber and an in-situ cleaning method of a hot element CVD apparatus. A hot element is disposed in a chamber is heated up to a temperature of 2000° C. or higher after the chamber is exhausted. Thereafter a cleaning gas which is decomposed and/or activated by the hot element to generate an activated species that converts the deposited film into gaseous substance is introduced into the chamber.

摘要翻译： 用于有效且完全地除去沉积在成膜室内的膜的方法和热元素CVD装置的原位清洗方法。 设置在室中的热元件在室耗尽之后被加热到高达2000℃或更高的温度。 此后，由热元件分解和/或激活以产生将沉积膜转化为气态物质的活化物质的清洁气体被引入室中。

公开(公告)号：US5605907A

公开(公告)日：1997-02-25

申请号：US531201

申请日：1995-09-19

申请人： Yasuhiro Kabasawa ,  Fumihiro Ozaki ,  Keiji Ishibashi ,  Takashi Hasegawa ,  Hitoshi Oinuma ,  Manabu Shirato ,  Katsuhiro Moriya ,  Toshiaki Ogawa ,  Satoshi Katayama ,  Shigeru Souda

发明人： Yasuhiro Kabasawa ,  Fumihiro Ozaki ,  Keiji Ishibashi ,  Takashi Hasegawa ,  Hitoshi Oinuma ,  Manabu Shirato ,  Katsuhiro Moriya ,  Toshiaki Ogawa ,  Satoshi Katayama ,  Shigeru Souda

IPC分类号： C07C13/18 ,  A61K31/015 ,  A61K31/13 ,  A61P21/00 ,  C07C327/46 ,  C07D471/04 ,  C07D521/00 ,  A61K31/435

CPC分类号： C07D231/12 ,  C07D233/56 ,  C07D249/08 ,  C07D471/04

摘要： To provide a novel cyclohexane derivative, a cyclohexane derivative is defined by the formula (I) or a pharmacologically acceptable salt thereof: ##STR1## (wherein R.sup.1 and R.sup.2 may be the same or different from each other and each represents hydrogen or lower alkyl; R.sup.3 represents optionally substituted aryl or optionally substituted heteroaryl; X represents oxygen or sulfur; and Y represents a group represented by the formula: ##STR2## or the like). The compound of the present invention is useful as a preventive and therapeutic agent for diseases against which a potassium channel opening action is efficacious.

摘要翻译： 为了提供新的环己烷衍生物，环己烷衍生物由式（I）或其药理学上可接受的盐定义：其中R 1和R 2可以彼此相同或不同，并且各自表示氢或 低级烷基; R 3表示任选取代的芳基或任选取代的杂芳基; X表示氧或硫; Y表示由下式表示的基团：等等）。 本发明的化合物可用作钾通道开放作用有效的疾病的预防和治疗剂。

公开(公告)号：US5444066A

公开(公告)日：1995-08-22

申请号：US211701

申请日：1994-04-26

申请人： Yasuhiro Kabasawa ,  Fumihiro Ozaki ,  Keiji Ishibashi ,  Takashi Hasegawa ,  Hitoshi Oinuma ,  Toshiaki Ogawa ,  Hideyuki Adachi ,  Hiroshi Katoh ,  Kohtarou Kodama ,  Hideto Ohara ,  Nobuyuki Mori ,  Norio Minami

发明人： Yasuhiro Kabasawa ,  Fumihiro Ozaki ,  Keiji Ishibashi ,  Takashi Hasegawa ,  Hitoshi Oinuma ,  Toshiaki Ogawa ,  Hideyuki Adachi ,  Hiroshi Katoh ,  Kohtarou Kodama ,  Hideto Ohara ,  Nobuyuki Mori ,  Norio Minami

IPC分类号： C07D231/12 ,  C07D233/92 ,  C07D233/95 ,  C07D471/04 ,  A61K31/435

CPC分类号： C07D233/92 ,  C07D471/04

摘要： The present invention provides a thioformamide derivative represented by the following general formula (I) or a pharmacologically acceptable salt thereof, which is highly safe, easy to use, and useful as an excellent hypotensive or heart disease remedy: ##STR1## wherein Y represents ##STR2## or the like [wherein R.sup.7 represents benzyloxy or the like; R.sup.11 and R.sup.12 each represent hydrogen, hydroxyl, benzoyloxy, benzyloxy, ##STR3## (wherein R.sup.14 and R.sup.15 each represent hydrogen, benzyl or the like) or the like];Z represents --CH.sub.2 -- or the like; A represents imidazolyl or imidazopyridyl which may have one or two substituents, or the like; R.sup.1 and R.sup.2 each represent hydrogen, lower alkyl or the like; and R.sup.3 and R.sup.4 each represent hydrogen, lower alkyl or the like.

摘要翻译： PCT No.PCT / JP92 / 01297 Sec。 371日期1994年04月26日 102（e）日期1994年4月26日PCT提交1992年10月6日PCT公布。 出版物WO93 / 08168 日本1994年4月29日。本发明提供由以下通式（I）表示的硫代甲酰胺衍生物或其药理学上可接受的盐，其是高度安全，易于使用的，并且可用作优异的降压药或心脏病药物： （I）其中Y表示酰氧基等; R 11和R 12各自表示氢，羟基，苯甲酰氧基，苄氧基，苯甲酰基等）等。 Z表示-CH 2 - 等; A表示可具有一个或两个取代基的咪唑基或咪唑并吡啶等; R 1和R 2各自表示氢，低级烷基等; R 3和R 4各自表示氢，低级烷基等。

公开(公告)号：US09708735B2

公开(公告)日：2017-07-18

申请号：US13526061

申请日：2012-06-18

申请人： Keiji Ishibashi ,  Yusuke Yoshizumi ,  Shugo Minobe

发明人： Keiji Ishibashi ,  Yusuke Yoshizumi ,  Shugo Minobe

IPC分类号： C30B29/54 ,  C30B33/00 ,  C30B29/40

CPC分类号： C30B33/00 ,  C30B21/02 ,  C30B29/403 ,  Y10T428/21 ,  Y10T428/24355

摘要： A group III nitride crystal substrate is provided, wherein, a uniform distortion at a surface layer of the crystal substrate is equal to or lower than 1.7×10−3, and wherein a plane orientation of the main surface has an inclination angle equal to or greater than −10° and equal to or smaller than 10° in a [0001] direction with respect to a plane including a c axis of the crystal substrate. A group III nitride crystal substrate suitable for manufacturing a light emitting device with a blue shift of an emission suppressed, an epilayer-containing group III nitride crystal substrate, a semiconductor device and a method of manufacturing the same can thereby be provided.

公开(公告)号：US08952494B2

公开(公告)日：2015-02-10

申请号：US13347717

申请日：2012-01-11

申请人： Keiji Ishibashi

发明人： Keiji Ishibashi

IPC分类号： H01L29/20 ,  H01L21/02 ,  C30B23/02 ,  C30B25/18 ,  C30B29/40 ,  H01L33/12 ,  H01L33/32

CPC分类号： H01L33/30 ,  C30B23/025 ,  C30B25/186 ,  C30B29/403 ,  H01L21/02013 ,  H01L21/02019 ,  H01L21/02024 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/02439 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/0254 ,  H01L21/02658 ,  H01L21/30621 ,  H01L24/32 ,  H01L29/2003 ,  H01L33/025 ,  H01L33/12 ,  H01L33/16 ,  H01L33/32 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/00014 ,  H01L2924/00

摘要： In a semiconductor device 100, it is possible to prevent C from piling up at a boundary face between an epitaxial layer 22 and a group III nitride semiconductor substrate 10 by the presence of 30×1010 pieces/cm2 to 2000×1010 pieces/cm2 of sulfide in terms of S and 2 at % to 20 at % of oxide in terms of O in a surface layer 12. By thus preventing C from piling up, a high-resistivity layer is prevented from being formed on the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10. Accordingly, it is possible to reduce electrical resistance at the boundary face between the epitaxial layer 22 and the group III nitride semiconductor substrate 10, and improve the crystal quality of the epitaxial layer 22. Consequently, it is possible to improve the emission intensity and yield of the semiconductor device 100.

摘要翻译： 在半导体器件100中，可以通过存在30×10 10片/ cm 2〜2000×10 10片/ cm 2的范围来防止C在外延层22和III族氮化物半导体衬底10之间的边界面堆积 表面层12中的S为硫化物，以O计为2at％〜20at％的氧化物。通过防止C堆积，可以防止在外延层之间的界面上形成高电阻率层 层22和III族氮化物半导体衬底10.因此，可以减小外延层22和III族氮化物半导体衬底10之间的边界面处的电阻，并且提高外延层22的晶体质量。结果 ，可以提高半导体装置100的发光强度和产量。

公开(公告)号：US20120223417A1

公开(公告)日：2012-09-06

申请号：US13469576

申请日：2012-05-11

申请人： Keiji Ishibashi ,  Yusuke Yoshizumi

发明人： Keiji Ishibashi ,  Yusuke Yoshizumi

IPC分类号： H01L29/20 ,  B32B5/16 ,  H01L21/66 ,  C01B21/06

CPC分类号： C30B33/00 ,  C09K3/1436 ,  C09K3/1463 ,  C30B29/403 ,  H01L21/02024 ,  H01L21/0237 ,  H01L21/02389 ,  H01L21/02395 ,  H01L21/02433 ,  H01L21/0254 ,  H01L33/16 ,  Y10T428/2982

摘要： A group III nitride crystal substrate is provided wherein, a uniform distortion at a surface layer of the crystal substrate is equal to or lower than 1.9×10−3, and wherein the main surface has a plane orientation inclined in a direction at an angle equal to or greater than 10° and equal to or smaller than 81° with respect to one of (0001) and (000-1) planes of the crystal substrate. A group III nitride crystal substrate suitable for manufacturing a light emitting device with a blue shift of an emission suppressed, an epilayer-containing group III nitride crystal substrate, a semiconductor device and a method of manufacturing the same can thereby be provided.

摘要翻译： 提供了一种III族氮化物晶体基板，其中，在晶体基板的表面层处的均匀的变形为1.9×10 -3以下，其中，所述主表面具有倾斜< 方向相对于晶体基板的（0001）和（000-1）面之一以等于或大于10°且等于或小于81°的角度。 因此，可以提供适合于制造抑制发射蓝移的发光器件的III族氮化物晶体衬底，含有外延层的III族氮化物晶体衬底，半导体器件及其制造方法。

公开(公告)号：US08242498B2

公开(公告)日：2012-08-14

申请号：US12953857

申请日：2010-11-24

申请人： Keiji Ishibashi ,  Fumitake Nakanishi

发明人： Keiji Ishibashi ,  Fumitake Nakanishi

IPC分类号： H01L21/00 ,  H01L21/31

CPC分类号： C30B29/403 ,  C30B25/02 ,  C30B29/406 ,  C30B33/00 ,  C30B33/12

摘要： A compound semiconductor substrate 10 according to the present invention is comprised of a Group III nitride and has a surface layer 12 containing a chloride of not less than 200×1010 atoms/cm2 and not more than 12000×1010 atoms/cm2 in terms of Cl and an oxide of not less than 3.0 at % and not more than 15.0 at % in terms of O, at a surface. The inventors conducted elaborate research and newly discovered that when the surface layer 12 at the surface of the compound semiconductor substrate 10 contained the chloride of not less than 200×1010 atoms/cm2 and not more than 12000×1010 atoms/cm2 in terms of Cl and the oxide of not less than 3.0 at % and not more than 15.0 at % in terms of O, Si was reduced at an interface between the compound semiconductor substrate 10 and an epitaxial layer 14 formed thereon and, as a result, the electric resistance at the interface was reduced.

摘要翻译： 根据本发明的化合物半导体衬底10由III族氮化物组成，其表面层12含有不低于200×10 10原子/ cm 2且不大于12000×10 10原子/ cm 2的氯化物 以及表面为O以上且3.0at％以上且15.0at％以下的氧化物。 本发明人进行了详细的研究，并且新发现，当化合物半导体基板10的表面上的表面层12含有不小于200×10 10原子/ cm 2且不大于12000×10 10原子/ cm 2的氯化物时，以Cl 并且氧化物以O计为3.0at％且不大于15.0at％时，在化合物半导体衬底10和形成在其上的外延层14之间的界面处Si还原，结果，电阻 在界面缩小。

公开(公告)号：US08228963B2

公开(公告)日：2012-07-24

申请号：US12715860

申请日：2010-03-02

申请人： Yohei Enya ,  Yusuke Yoshizumi ,  Hideki Osada ,  Keiji Ishibashi ,  Katsushi Akita ,  Masaki Ueno

发明人： Yohei Enya ,  Yusuke Yoshizumi ,  Hideki Osada ,  Keiji Ishibashi ,  Katsushi Akita ,  Masaki Ueno

IPC分类号： H01S5/00

CPC分类号： H01L33/18 ,  B82Y20/00 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02573 ,  H01L21/0262 ,  H01L33/32 ,  H01S5/20 ,  H01S5/2009 ,  H01S5/3202 ,  H01S5/34333

摘要： A gallium nitride-based semiconductor optical device is provided that includes an indium-containing gallium nitride-based semiconductor layer that exhibit low piezoelectric effect and high crystal quality. The gallium nitride-based semiconductor optical device 11a includes a GaN support base 13, a GaN-based semiconductor region 15, and well layers 19. A primary surface 13a tilts from a surface orthogonal to a reference axis that extends in a direction from one crystal axis of the m-axis and the a-axis of GaN toward the other crystal axis. The tilt angle AOFF is 0.05 degree or more to less than 15 degrees. The angle AOFF is equal to the angle defined by a vector VM and a vector VN. The inclination of the primary surface is shown by a typical m-plane SM and m-axis vector VM. The GaN-based semiconductor region 15 is provided on the primary surface 13a. In the well layers 19 in an active layer 17, both the m-plane and the a-plane of the well layers 19 tilt from a normal axis AN of the primary surface 13a. The indium content of the well layers 19 is 0.1 or more.

摘要翻译： 提供一种氮化镓系半导体光学元件，其包括显示低压电效应和高结晶质量的含铟氮化镓系半导体层。 氮化镓系半导体光学元件11a包括GaN支撑基底13，GaN基半导体区域15以及阱层19.初级表面13a从与从一个晶体的方向延伸的参考轴正交的表面倾斜 m轴的a轴和另一个晶轴的GaN的a轴。 倾角AOFF为0.05度以上至小于15度。 角度AOFF等于由矢量VM和矢量VN定义的角度。 主表面的倾角由典型的m面SM和m轴矢量VM表示。 GaN基半导体区域15设置在主表面13a上。 在有源层17的阱层19中，阱层19的m面和a面都从主面13a的法线轴AN倾斜。 阱层19的铟含量为0.1以上。

公开(公告)号：US20120184108A1

公开(公告)日：2012-07-19

申请号：US13437221

申请日：2012-04-02

申请人： Keiji Ishibashi ,  Hidenori Mikami ,  Naoki Matsumoto

发明人： Keiji Ishibashi ,  Hidenori Mikami ,  Naoki Matsumoto

IPC分类号： H01L21/302

CPC分类号： H01L21/02021 ,  C30B29/403 ,  C30B33/00 ,  H01L24/32 ,  H01L33/0075 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/12041 ,  H01L2924/12042 ,  Y10S438/928 ,  Y10S438/959 ,  Y10S438/977 ,  H01L2924/00014 ,  H01L2924/00

摘要： A nitride semiconductor wafer is planar-processed by grinding a bottom surface of the wafer, etching the bottom surface by, e.g., KOH for removing a bottom process-induced degradation layer, chamfering by a rubber whetstone bonded with 100 wt %-60 wt % #3000-#600 diamond granules and 0 wt %-40 wt % oxide granules, grinding and polishing a top surface of the wafer, etching the top surface for eliminating a top process-induced degradation layer and maintaining a 0.5 μm-10 μm thick edge process-induced degradation layer.