公开(公告)号：US10573612B2

公开(公告)日：2020-02-25

申请号：US16104720

申请日：2018-08-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jaspreet S. Gandhi ,  James M. Derderian ,  Sameer S. Vadhavkar ,  Jian Li

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/367 ,  H01L23/34 ,  H01L21/78 ,  H01L25/065 ,  H01L25/00

Abstract: Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate.

公开(公告)号：US20190114280A1

公开(公告)日：2019-04-18

申请号：US16215719

申请日：2018-12-11

Applicant: Micron Technology, Inc.

Inventor： Jian Li

IPC: G06F13/40 ,  G06F13/16

Abstract: The present disclosure relates generally to semiconductor memory and methods, and more particularly, to apparatuses, and methods for controlling logic die circuitries. One example apparatus comprises a logic die including a first serialization/deserialization (SERDES) component and a second SERDES component coupled to the logic die, and a switch component coupled to the first SERDES component and the second SERDES component configured to activate one of the number of SERDES components.

公开(公告)号：US10134655B2

公开(公告)日：2018-11-20

申请号：US15874406

申请日：2018-01-18

Applicant: Micron Technology, Inc.

Inventor： Steven Groothuis ,  Jian Li ,  Shijian Luo

IPC: H01L21/00 ,  H01L23/02 ,  H01L23/367 ,  H01L25/065 ,  H01L23/48 ,  H01L21/56 ,  H01L23/13 ,  H01L23/498 ,  H01L21/48

Abstract: Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. An uppermost semiconductor die of the stack of semiconductor dice located on a side of the stack of semiconductor dice opposite the substrate may be a heat-generating component configured to generate more heat than each other semiconductor die of the stack of semiconductor dice. Electrical connectors may extend directly from the uppermost semiconductor die to the substrate.

公开(公告)号：US20180308785A1

公开(公告)日：2018-10-25

申请号：US16020567

申请日：2018-06-27

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L23/44 ,  H01L23/367 ,  H01L25/00 ,  H01L23/00 ,  H01L25/18 ,  H01L23/373 ,  H01L21/56

CPC classification number: H01L23/44 ,  H01L21/50 ,  H01L21/563 ,  H01L23/04 ,  H01L23/3675 ,  H01L23/3736 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/1134 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/2939 ,  H01L2224/29393 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/8388 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/156 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1815 ,  H01L2924/0715 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/00

Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

公开(公告)号：US09899293B2

公开(公告)日：2018-02-20

申请号：US15401762

申请日：2017-01-09

Applicant: Micron Technology, Inc.

Inventor： Steven Groothuis ,  Jian Li ,  Shijian Luo

IPC: H01L21/00 ,  H01L21/44 ,  H01L23/367 ,  H01L25/065 ,  H01L21/56 ,  H01L23/48 ,  H01L21/48

CPC classification number: H01L23/3675 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/13 ,  H01L23/367 ,  H01L23/481 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/18161 ,  H01L2924/00

Abstract: Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. An uppermost semiconductor die of the stack of semiconductor dice located on a side of the stack of semiconductor dice opposite the substrate may be a heat-generating component configured to generate more heat than each other semiconductor die of the stack of semiconductor dice. Electrical connectors may extend directly from the uppermost semiconductor die to the substrate. A heat sink may be located on a side of the uppermost semiconductor die opposite the substrate. A passivation material may be located between the uppermost semiconductor die and the heat sink.

公开(公告)号：US09691746B2

公开(公告)日：2017-06-27

申请号：US14330805

申请日：2014-07-14

Applicant: Micron Technology, Inc.

Inventor： Sameer S. Vadhavkar ,  Xiao Li ,  Steven K. Groothuis ,  Jian Li ,  Jaspreet S. Gandhi ,  James M. Derderian ,  David R. Hembree

IPC: H01L25/00 ,  H01L21/56 ,  H01L23/00 ,  H01L23/04 ,  H01L21/50 ,  H01L25/065 ,  H01L23/367 ,  H01L23/44 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/50 ,  H01L21/563 ,  H01L23/04 ,  H01L23/3675 ,  H01L23/44 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/1134 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/2919 ,  H01L2224/29191 ,  H01L2224/2929 ,  H01L2224/2939 ,  H01L2224/29393 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/83101 ,  H01L2224/83102 ,  H01L2224/83104 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/8388 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/156 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1815 ,  H01L2924/0715 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/0665 ,  H01L2924/00

Abstract: Method for packaging a semiconductor die assemblies. In one embodiment, a method is directed to packaging a semiconductor die assembly having a first die and a plurality of second dies arranged in a stack over the first die, wherein the first die has a peripheral region extending laterally outward from the stack of second dies. The method can comprise coupling a thermal transfer structure to the peripheral region of the first die and flowing an underfill material between the second dies. The underfill material is flowed after coupling the thermal transfer structure to the peripheral region of the first die such that the thermal transfer structure limits lateral flow of the underfill material.

公开(公告)号：US09543274B2

公开(公告)日：2017-01-10

申请号：US14605466

申请日：2015-01-26

Applicant: Micron Technology, Inc.

Inventor： Steven Groothuis ,  Jian Li ,  Shijian Luo

IPC: H01L21/00 ,  H01L23/02 ,  H01L25/065 ,  H01L23/48 ,  H01L21/56 ,  H01L23/13

CPC classification number: H01L23/3675 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/13 ,  H01L23/367 ,  H01L23/481 ,  H01L23/49827 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/18161 ,  H01L2924/00

Abstract: Semiconductor device packages in accordance with this disclosure may include a substrate and a stack of semiconductor dice attached to the substrate. The stack of semiconductor dice may include vias extending through each semiconductor die of the stack for electrically interconnecting the semiconductor dice in the stack to one another and to the substrate. Another semiconductor die may be electrically connected to the stack of semiconductor dice and may be located on a side of the stack of semiconductor dice opposing the substrate. The other semiconductor die may be a heat-generating component configured to generate more heat than each semiconductor die of the stack of semiconductor dice. Electrical connectors may be located laterally adjacent to the vias and may form electrical connections between the substrate and the other semiconductor die in isolation from integrated circuitry of the semiconductor dice in the stack.

Abstract translation: 根据本公开的半导体器件封装可以包括衬底和附接到衬底的半导体管芯堆叠。 半导体晶片的堆叠可以包括延伸穿过堆叠的每个半导体管芯的通孔，用于将堆叠中的半导体管芯彼此彼此和衬底电互连。 另一个半导体管芯可以电连接到半导体管芯的堆叠，并且可以位于与衬底相对的半导体管芯堆叠的一侧。 另一个半导体管芯可以是被配置成比半导体管芯堆叠的每个半导体管芯产生更多的热量的发热部件。 电连接器可以位于横向邻近通孔的位置，并且可以在堆叠中的半导体裸片的集成电路之外形成衬底和另一半导体管芯之间的电连接。

公开(公告)号：US09515002B2

公开(公告)日：2016-12-06

申请号：US14617375

申请日：2015-02-09

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jaspreet S Gandhi ,  James M. Derderian ,  Sameer S Vadhavkar ,  Jian Li

IPC: H01L21/44 ,  H01L23/34 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L24/06 ,  H01L21/78 ,  H01L23/34 ,  H01L23/3677 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0362 ,  H01L2224/03622 ,  H01L2224/05015 ,  H01L2224/05025 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/06519 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06589

Abstract: Apparatuses and methods for providing thermal pathways from a substrate to a thermal bonding pad. The thermal pathways may be metal extensions of the thermal bonding pad that are disposed in channels formed in a backside passivation layer underneath the thermal bonding pad, and may be in direct contact with an underlying substrate. The thermal pathways may provide improved thermal dissipation from the substrate.

Abstract translation: 用于提供从衬底到热粘合垫的热路径的装置和方法。 热路径可以是热粘合垫的金属延伸部，其设置在形成在热粘合垫下方的背侧钝化层中的通道中，并且可以与下面的基底直接接触。 热路径可以提供从衬底改善的热耗散。

公开(公告)号：US20160322340A1

公开(公告)日：2016-11-03

申请号：US14700222

申请日：2015-04-30

Applicant: Micron Technology, Inc.

Inventor： Jian Li ,  Steven K. Groothuis

IPC: H01L25/18 ,  H01L23/498 ,  H01L23/367 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L23/538

CPC classification number: H01L25/18 ,  H01L21/6835 ,  H01L23/055 ,  H01L23/13 ,  H01L23/3675 ,  H01L23/3677 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/33 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68331 ,  H01L2224/0401 ,  H01L2224/05082 ,  H01L2224/05147 ,  H01L2224/05171 ,  H01L2224/05644 ,  H01L2224/05664 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/92225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15793 ,  H01L2924/16251 ,  H01L2924/16747 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Semiconductor die assemblies and methods of forming the same are described herein. As an example, a semiconductor die assembly may include a thermally conductive casing, a first face of a logic die coupled to the thermally conductive casing to form a thermal path that transfers heat away from the logic die to the thermally conductive casing, a substrate coupled to a second face of the logic die, and a die embedded at least partially in a cavity of the substrate.

Abstract translation: 本文描述了半导体管芯组件及其形成方法。 作为示例，半导体管芯组件可以包括导热壳体，耦合到导热壳体的逻辑管芯的第一面以形成将热量从逻辑管芯传导到导热壳体的热路径;衬底耦合 到达逻辑管芯的第二面，以及至少部分地嵌入衬底的空腔中的管芯。

公开(公告)号：US20160181125A1

公开(公告)日：2016-06-23

申请号：US15059076

申请日：2016-03-02

Applicant: Micron Technology, Inc.

Inventor： Jian Li ,  Steven K. Groothuis ,  Michel Koopmans

IPC: H01L21/48 ,  H01L23/42 ,  H01L21/56 ,  H01L23/373 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L21/4882 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3731 ,  H01L23/3738 ,  H01L23/42 ,  H01L23/4275 ,  H01L23/4334 ,  H01L23/49827 ,  H01L23/5385 ,  H01L24/09 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16257 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/15311

Abstract: Stacked semiconductor die assemblies with thermal spacers and associated systems and methods are disclosed herein. In one embodiment, a semiconductor die assembly can include a thermally conductive casing defining a cavity, a stack of first semiconductor dies within the cavity, and a second semiconductor die stacked relative to the stack of first dies and carried by a package substrate. The semiconductor die assembly further includes a thermal spacer disposed between the package substrate and the thermally conductive casing. The thermal spacer can include a semiconductor substrate and plurality of conductive vias extending through the semiconductor substrate and electrically coupled to the stack of first semiconductor dies, the second semiconductor die, and the package substrate.