公开(公告)号：US10073314B2

公开(公告)日：2018-09-11

申请号：US15509526

申请日：2015-08-31

Applicant: Sharp Kabushiki Kaisha

Inventor： Sumio Katoh ,  Naoki Ueda

IPC: G02F1/1368 ,  G02F1/1362 ,  G02F1/1343 ,  H01L27/12 ,  H01L29/786

CPC classification number: G02F1/1368 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/136209 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/134372 ,  G02F2001/136218 ,  G02F2201/121 ,  G02F2201/123 ,  G02F2202/02 ,  G02F2202/10 ,  H01L21/28 ,  H01L27/1225 ,  H01L27/1248 ,  H01L29/41733 ,  H01L29/786 ,  H01L29/7869

Abstract: A semiconductor device includes: a first metal layer including a gate electrode; a first insulating layer provided on the first metal layer; an oxide semiconductor layer provided on the first insulating layer; a second insulating layer provided on the oxide semiconductor layer; a second metal layer provided on the oxide semiconductor layer and the second insulating layer, the second metal layer including a source electrode; a third insulating layer provided on the second metal layer; and a first transparent electrode layer provided on the third insulating layer. The oxide semiconductor layer includes a first portion lying above the gate electrode and a second portion extending from the first portion so as to lie across an edge of the gate electrode on the drain electrode side. The third insulating layer does not include an organic insulating layer. The second insulating layer and the third insulating layer have a first contact hole which overlaps the second portion of the oxide semiconductor layer when viewed in a normal direction of the substrate. The first transparent electrode layer includes a transparent electrically-conductive layer which is in contact with the second portion of the oxide semiconductor layer in the first contact hole.

公开(公告)号：US10061170B2

公开(公告)日：2018-08-28

申请号：US15662858

申请日：2017-07-28

Applicant: Japan Display Inc.

Inventor： Shuichi Osawa ,  Yoshikatsu Imazeki ,  Yoichi Kamijo ,  Yoshihiro Watanabe

IPC: H01L21/48 ,  G02F1/1362 ,  H01L21/285 ,  G02F1/1337 ,  B32B7/04 ,  H01L21/02 ,  B23K26/00

CPC classification number: G02F1/136227 ,  B23K26/57 ,  B32B3/266 ,  B32B7/04 ,  B32B7/14 ,  B32B15/20 ,  B32B17/00 ,  B32B27/06 ,  B32B27/308 ,  B32B27/36 ,  B32B2250/44 ,  B32B2264/105 ,  B32B2307/20 ,  B32B2307/202 ,  B32B2307/204 ,  B32B2307/206 ,  B32B2307/412 ,  B32B2307/416 ,  B32B2307/42 ,  B32B2307/546 ,  B32B2307/732 ,  B32B2457/20 ,  B32B2457/202 ,  G02F1/133711 ,  G02F1/1339 ,  G02F1/136213 ,  G02F2001/133388 ,  H01L21/02063 ,  H01L21/28506

Abstract: According to one embodiment, a method of manufacturing an electronic device, includes preparing a first substrate including a first basement and a first conductive layer, and a second substrate includes a second basement and a second conductive layer, opposing the first conductive layer and spaced from the first conductive layer, providing a protection layer on the second substrate, forming a first hole penetrating the second substrate by irradiating the second substrate with a laser beam in a position overlapping the protection layer, removing the protection layer and forming a connecting material electrically connecting the first conductive layer and the second conductive layer to each other via the first hole after removing the protection layer.

公开(公告)号：US10054831B2

公开(公告)日：2018-08-21

申请号：US15139655

申请日：2016-04-27

Applicant: Xiamen Tianma Micro-electronics Co., Ltd. ,  Tianma Micro-electronics Co., Ltd.

Inventor： Binbin Chen

IPC: G02F1/1345 ,  G02F1/1333 ,  G02F1/1362 ,  G02F1/1335 ,  G02F1/1368 ,  H01L27/02 ,  H01L27/12 ,  H01L29/786

CPC classification number: G02F1/136204 ,  G02F1/133345 ,  G02F1/133351 ,  G02F1/13338 ,  G02F1/133512 ,  G02F1/133514 ,  G02F1/13458 ,  G02F1/136209 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136218 ,  G02F2001/13629 ,  G02F2001/136295 ,  H01L27/0292 ,  H01L27/1244 ,  H01L27/1248 ,  H01L27/1259 ,  H01L27/3272 ,  H01L27/3276 ,  H01L29/78633

Abstract: An array substrate and an array substrate fabrication method are provided. The array substrate comprises a base substrate, a first conductive layer, a first passivation layer including a plurality of first through-holes. a light-shielding layer including a plurality of first metal wires arranged in parallel, a second passivation layer including a plurality of second through-holes, and a first metal layer including a plurality of second metal wires arranged in parallel and one-to-one corresponding to the plurality of first metal wires. The first metal wire is electrically connected to the first conductive layer through at least one first through-hole, and the second metal wire is electrically connected to the corresponding first metal wire through at least one second through-hole. The array substrate includes a display region and a non-display region, and the first through-holes and the second through-holes are formed at the non-display region of the array substrate.

公开(公告)号：US20180231820A1

公开(公告)日：2018-08-16

申请号：US15758142

申请日：2015-08-14

Applicant: BOE TECHNOLOGY GROUP CO., LTD. ,  BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Lianjie Qu

IPC: G02F1/1343 ,  G02F1/1362 ,  G02F1/1333 ,  G02F1/1368

CPC classification number: G02F1/13439 ,  G02F1/133345 ,  G02F1/136209 ,  G02F1/136227 ,  G02F1/13624 ,  G02F1/1368 ,  G02F2001/134345 ,  G02F2201/123 ,  G02F2203/02

Abstract: An array substrate, a fabrication method of the array substrate, and a display device including the array substrate are provided. The array substrate includes a first electrode (54) including a plurality of first sub-electrodes, a second electrode (3) including a plurality of second sub-electrodes, and an insulating layer (6) disposed between the first electrode (54) and the second electrode (3). A plurality of via holes (61) are formed in the insulating layer (6), and the plurality of the second sub-electrodes are electrically connected to the plurality of the first sub-electrodes correspondingly through the plurality of the via holes (61). The array substrate further includes a light compensating structure (4) disposed under an uneven portion of the insulating layer (6) to locally improve an exposure efficiency in a photolithographic process for forming the second electrode (3).

公开(公告)号：US20180217459A1

公开(公告)日：2018-08-02

申请号：US15125194

申请日：2016-07-29

Applicant: Shenzhen China Star Optoelectronics Technology Co. Ltd.

Inventor： Yue WU ,  Weina YONG ,  Bangyin PENG

IPC: G02F1/1362 ,  G02F1/1368 ,  H01L27/12

CPC classification number: G02F1/136227 ,  G02F1/133707 ,  G02F1/134309 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2201/40 ,  H01L27/124

Abstract: The present disclosure provides an array substrate and a liquid crystal display panel, the array substrate includes a plurality of gate lines spaced in parallel and a plurality of data lines spaced in parallel, a plurality of pixel areas are orthogonally disposed the plurality of gate lines and the plurality of data lines; the plurality of gate lines and the plurality of data line are insulated orthogonal, the each pixel area includes a TFT switch, a pixel electrode, the TFT switch connects the gate line and data line of the pixel area where the TFT switch is located, a via hole is arranged in the pixel electrode, the via hole is arranged adjacent to the TFT switch, the pixel electrode is electrically connected through the via hole and the TFT switch arranged in the pixel electrode.

公开(公告)号：US20180217453A1

公开(公告)日：2018-08-02

申请号：US14897777

申请日：2015-11-05

Applicant: Shenzhen China Star Optoelectronics Technology Co. Ltd. ,  Wuhan China Star Optoelectronics Technology Co. Ltd.

Inventor： Yafeng LI ,  Jianhong LIN

IPC: G02F1/1343 ,  G02F1/1362 ,  G02F1/1368

CPC classification number: G02F1/134363 ,  G02F1/133514 ,  G02F1/13394 ,  G02F1/136209 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2001/13396 ,  G02F2001/134318 ,  G02F2001/134345 ,  G02F2001/13685 ,  G02F2201/121 ,  G02F2201/122 ,  G02F2201/123 ,  G02F2202/104 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1248 ,  H01L29/78633 ,  H01L29/78675

Abstract: Provided is an LTPS array substrate and a liquid crystal display panel, wherein the LTPS array substrate comprises: a first common electrode layer; a passivation layer, which is formed on the first common electrode layer, and has a first via hole formed therein; a pixel electrode layer, which is formed on the passivation layer; and a second common electrode layer, which is formed on the passivation layer, located between pixel electrodes corresponding to two adjacent sub-pixels in the pixel electrode layer, electrically isolated from the pixel electrode layer, and electrically connected to the first common electrode layer through the first via hole. The array substrate is capable of significantly enhancing the intensity of an electric field at an edge region of the adjacent sub-pixels, thereby increasing the transmittance at this region.

公开(公告)号：US20180212043A1

公开(公告)日：2018-07-26

申请号：US15327470

申请日：2016-12-29

Applicant: Wuhan China Star Optoelectronics Technology Co. Ltd.

Inventor： Tao Sun

IPC: H01L29/66 ,  H01L27/12 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/66765 ,  B81C2201/0108 ,  G02F1/133345 ,  G02F1/136227 ,  G03F1/80 ,  G03F5/16 ,  G03F7/0035 ,  G03F7/0041 ,  G03F7/422 ,  G03F7/427 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/0274 ,  H01L21/205 ,  H01L21/2855 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/31058 ,  H01L21/31133 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32 ,  H01L21/32134 ,  H01L21/32139 ,  H01L27/1214 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/518 ,  H01L29/78603 ,  H01L29/78609 ,  H01L29/78618 ,  H01L29/78669 ,  H01L2924/13069 ,  H05K2201/0338 ,  H05K2201/0361

Abstract: Disclosed is a method for manufacturing a thin film transistor. The method includes steps of etching a second metal layer and a semiconductor layer to form a boundary region of a thin film transistor; etching the second metal layer again to form a source, a drain and a back channel region of the thin film transistor; removing residual photoresist via an ashing procedure; and etching the semiconductor layer again to form a conductive channel of the thin film transistor. According to the method, the electric leakage problem of thin film transistor due to diffusion of copper and contamination of organic stripping liquid can be eliminated.

公开(公告)号：US20180212009A1

公开(公告)日：2018-07-26

申请号：US15852547

申请日：2017-12-22

Applicant: Japan Display Inc.

Inventor： Kazuhiro ODAKA

IPC: H01L27/32 ,  H01L51/50 ,  H01L51/52 ,  G02F1/1333 ,  G02F1/1362

CPC classification number: H01L27/3258 ,  G02F1/133345 ,  G02F1/136227 ,  H01L27/124 ,  H01L27/3246 ,  H01L27/3262 ,  H01L27/3276 ,  H01L51/5012 ,  H01L51/5206 ,  H01L51/5246

Abstract: A display device in an embodiment according to the present invention includes a display region above a first substrate, the display region includes, a plurality of a pixels, a transistor arranged to each of the plurality of the pixels, a light emitting element arranged to each of plurality of the pixels, an interlayer insulating layer above the transistor, and a planarization film above the inter layer insulating layer, a terminal region above the first substrate in a periphery region of the display region, the terminal region including, a plurality of terminals, each of which includes a first conductive layer above the interlayer insulating layer, the planarization film is arranged in a side part of the first conductive layer, and an inorganic insulating layer covering an upper surface of planarization film and an end part of the first conductive layer.

公开(公告)号：US20180210249A1

公开(公告)日：2018-07-26

申请号：US15326551

申请日：2017-01-07

Applicant: Wuhan China Star Optoelectronics Technology Co., Ltd.

Inventor： Liang MA ,  Mang ZHAO

IPC: G02F1/1368 ,  H01L29/786 ,  G02F1/1362

CPC classification number: G02F1/1368 ,  G02F1/134363 ,  G02F1/1362 ,  G02F1/136209 ,  G02F1/136213 ,  G02F1/136227 ,  G02F2001/134372 ,  G02F2001/13685 ,  H01L29/78609 ,  H01L29/78624 ,  H01L29/78633 ,  H01L29/7869 ,  H01L29/78696

Abstract: The present disclosure relates to a display panel including a first substrate, a second substrate, a liquid crystal layer between the first substrate and the second substrate, a masking layer on the first substrate, a buffering layer arranged on the masking layer and the first substrate, a first semiconductor layer on the buffering layer, and an active layer on the first semiconductor layer and the buffering layer. The present disclosure also relates to a display device. With such configuration, the leakage current of the TFTs may be reduced, which also reduces the cross-talk and the flicker of the liquid crystal panel.

公开(公告)号：US20180197883A1

公开(公告)日：2018-07-12

申请号：US15688304

申请日：2017-08-28

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Hongfei CHENG

IPC: H01L27/12 ,  G02F1/1362

CPC classification number: H01L27/124 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/136218 ,  G02F2201/121 ,  H01L27/1255

Abstract: An array substrate is provided, which includes: a base substrate; a plurality of gate lines, a plurality of data lines and a plurality of common electrode lines arranged on the base substrate; a pixel electrode arranged at each region defined by adjacent gate lines and adjacent data lines; and a TFT arranged at a position in proximity to a junction between each of the gate lines and the corresponding data line. A drain electrode of the TFT is electrically connected to the pixel electrode through a via-hole. Each common electrode line includes a primary electrode line extending in a direction identical to an extension direction of the gate line, and a secondary electrode line connected in parallel to the primary electrode line. The secondary electrode line includes at least one first secondary electrode line arranged between the via-hole and the data line.