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    SYNCHRONIZING SYSTEMS ON A CHIP USING A SHARED CLOCK
    76.
    发明公开
    SYNCHRONIZING SYSTEMS ON A CHIP USING A SHARED CLOCK 审中-公开

    公开(公告)号：US20230393609A1

    公开(公告)日：2023-12-07

    申请号：US18236732

    申请日：2023-08-22

    Applicant: Samuel Ahn ,  Jason Heger ,  Dmitry Ryuma

    Inventor： Samuel Ahn ,  Jason Heger ,  Dmitry Ryuma

    IPC: G06F1/12 ,  G06F1/04 ,  G06F13/42

    CPC classification number: G06F1/12 ,  G06F1/04 ,  G06F13/4221 ,  G06F2213/0026

    Abstract: An electronic eyewear device includes first and second systems on a chip (SoCs) having independent time bases that are synchronized by generating a common clock signal from a clock generator of the first SoC and simultaneously applying the common clock signal to a first counter of the first SoC and a second counter of the second SoC whereby the first counter and the second counter count clock edges of the common clock. The clock counts are shared through an interface between the first SoC and the second SoC and compared to each other. When the clock counts are different, a clock count of the first counter or the second counter is adjusted to cause the clock counts to match each other. The adjusted clock count is synchronized to the respective clocks of the first and second SoCs, thus synchronizing the first and second SoCs to each other.

    System and method for testing non-volatile memory express storage devices
    77.
    发明授权
    System and method for testing non-volatile memory express storage devices 有权

    公开(公告)号：US11836059B1

    公开(公告)日：2023-12-05

    申请号：US17549463

    申请日：2021-12-13

    Applicant: SANBlaze Technology, Inc.

    Inventor： Stephen F. Shirron ,  B. Vincent Asbridge

    IPC: G06F11/22 ,  G06F13/16 ,  G06F13/42

    CPC classification number: G06F11/221 ,  G06F11/2268 ,  G06F13/1668 ,  G06F13/4221 ,  G06F2213/0026

    Abstract: PCIe devices may be connected to a test system for development, quality assurance, manufacturing, design validation, qualification, certification, and other testing. PCIe bus or other unexpected errors can avoid direct capture by the test system. Inserting a PCIe analyzer can capture a trace of PCIe bus data around any specific trigger. Due to the high volume and speed of data crossing the data bus when testing multiple devices, finding a correct trigger for an analyzer trace capture is akin to finding a needle in a haystack. By configuring a specific trigger pattern that the test system can send across the PCIe bus without impacting any of the devices under test, the test system can trigger the analyzer at the precise time needed to capture a PCIe bus data trace around the error.

    System and method of enhancing performances of information handling systems by utilizing graphics processing units
    78.
    发明授权
    System and method of enhancing performances of information handling systems by utilizing graphics processing units 有权

    公开(公告)号：US11829216B2

    公开(公告)日：2023-11-28

    申请号：US17208677

    申请日：2021-03-22

    Applicant: Dell Products L.P.

    Inventor： Thomas Alexander Shows ,  Yi-Ting Wang

    IPC: G06F1/20 ,  G06F13/42 ,  G06T1/20

    CPC classification number: G06F1/206 ,  G06F13/4221 ,  G06T1/20 ,  G06F2213/0026

    Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may determine a temperature value associated with a discrete graphics processing unit (dGPU); if the temperature value is below a threshold temperature value: configure an information handling system (IHS) to utilize the dGPU for processing graphics workloads of the IHS; disable an integrated graphics processing unit (iGPU) from processing any of the graphics workloads; and provide an amount of power utilized by the iGPU to a processor of the IHS; and if the temperature value is not below the threshold temperature value: determine that the iGPU is disabled; configure the IHS to utilize the iGPU for processing a portion of the graphics workloads; and enable the iGPU to process the portion of the graphics workloads; and remove the amount of power utilized by the iGPU from the at least one processor.

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