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公开(公告)号：US11991826B2
公开(公告)日：2024-05-21
申请号：US17602527
申请日：2020-04-10
Applicant: DONGWOO FINE-CHEM CO., LTD.
Inventor： Jongmin Kim , Dong Pil Park , Yoonho Huh
IPC: H05K1/11 , H01Q1/24 , H01Q1/38 , H01Q1/48 , H05K1/02 , H05K1/16 , H05K1/18 , H05K3/00 , H05K3/28 , H05K3/36 , H05K3/40
CPC classification number: H05K1/118 , H01Q1/38 , H05K1/0218 , H05K1/189 , H05K3/281 , H05K2201/09327
Abstract: A flexible printed circuit board includes a power wiring layer transmitting power and a signal wiring layer insulated and stacked over or under the power wiring layer. The flexible printed circuit board may also include an upper wiring layer and a lower wiring layer insulated and stacked each other, and the power wiring layer and the signal wiring layer are provided between the upper wiring layer and the lower wiring layer.
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公开(公告)号：US20180263111A1
公开(公告)日：2018-09-13
申请号：US15758460
申请日：2016-08-11
Applicant: ZF Friedrichshafen AG
Inventor： Michael Sperber , Wilfried Lassmann , Dirk Schramm
CPC classification number: H05K1/0265 , H05K1/0206 , H05K1/0209 , H05K1/021 , H05K1/115 , H05K1/185 , H05K2201/064 , H05K2201/066 , H05K2201/09327 , H05K2201/10015 , H05K2201/10053
Abstract: A multifunctional high current circuit board includes a high current-carrying current-conducting layer and a switching layer, which is connected to at least one heat source, wherein high current-carrying potentials are conducted into the switching layer.
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公开(公告)号：US09839131B2
公开(公告)日：2017-12-05
申请号：US14918678
申请日：2015-10-21
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Bruce J. Chamberlin , Andreas Huber , Harald Huels , Thomas Strach , Thomas-Michael Winkel
CPC classification number: H05K1/184 , B23K1/0016 , H05K1/0298 , H05K1/092 , H05K1/111 , H05K1/113 , H05K1/116 , H05K1/162 , H05K1/165 , H05K1/167 , H05K1/185 , H05K1/186 , H05K3/0047 , H05K3/3447 , H05K3/429 , H05K3/46 , H05K3/4644 , H05K3/4697 , H05K2201/093 , H05K2201/09309 , H05K2201/09327 , H05K2201/09345 , H05K2201/09381 , H05K2201/09518 , H05K2201/09545 , H05K2201/096 , H05K2201/09845 , H05K2201/10 , H05K2201/10015 , H05K2201/10022 , H05K2201/1003 , H05K2201/1006 , H05K2201/10174
Abstract: Embedding a discrete electrical device in a printed circuit board (PCB) includes: providing a vertical via as a blind hole from a horizontal surface of the PCB to an electrically conductive structure in a first layer, the first layer being one layer of a first core section of a plurality of core sections vertically arranged above each other, each core section including lower and upper conductive layers, and a non-conductive layer in between; inserting the electrical device into the via, with the device extending within at least two of the core sections; establishing a first electrical connection between a first electrical device contact device and the electrically conductive structure in the first layer; and establishing a second electrical connection between a second electrical device contact and a second layer, the second layer being one of the electrically conductive layers of a second horizontal core section.
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公开(公告)号：US09510439B2
公开(公告)日：2016-11-29
申请号：US14297825
申请日：2014-06-06
Applicant: Honeywell International Inc.
Inventor： Kenneth Lee Martin , Lucilo De La Torre , James Frederick Peterson , Jonathan Cole
IPC: G06F17/50 , H01L23/00 , H05K1/02 , H05K1/11 , H01L23/535 , H01L21/48 , H01L23/48 , H01L23/522
CPC classification number: H05K1/0237 , G06F17/5077 , H01L21/486 , H01L23/481 , H01L23/5226 , H01L23/535 , H01L2924/0002 , H05K1/0218 , H05K1/115 , H05K2201/0723 , H05K2201/09309 , H05K2201/09327 , H05K2201/09536 , H05K2201/09972 , H01L2924/00
Abstract: Systems and methods described herein provide for a circuit board having multiple fault containment regions therein. The circuit board includes a first fault containment region defined, at least in part, by first and second metal layers coupled to ground. The first fault containment region includes a first signal layer between the first and second metal layers, a third metal layer between the first and second metal layers, the third metal layer connected to the first signal layer to provide a return path for the first signal layer, and a fourth metal layer between the first and second metal layers, the fourth metal layer connected to the first signal layer to provide power to the first signal layer. The circuit board also includes a second fault containment region in a plurality of layers below the first fault containment region.
Abstract translation: 本文所述的系统和方法提供了其中具有多个故障容纳区域的电路板。 电路板包括第一故障容纳区域，该第一故障容纳区域至少部分地由耦合到地面的第一和第二金属层限定。 第一故障容纳区域包括在第一和第二金属层之间的第一信号层，在第一和第二金属层之间的第三金属层，第三金属层连接到第一信号层以提供第一信号层的返回路径 以及在第一和第二金属层之间的第四金属层，第四金属层连接到第一信号层以向第一信号层提供电力。 电路板还包括在第一故障容纳区域下方的多个层中的第二故障容纳区域。
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公开(公告)号：US09060423B2
公开(公告)日：2015-06-16
申请号：US13349971
申请日：2012-01-13
Applicant: Satoshi Mizuno , Masafumi Oyama , Akira Arahata
Inventor： Satoshi Mizuno , Masafumi Oyama , Akira Arahata
CPC classification number: H05K1/0218 , H05K1/0228 , H05K1/025 , H05K2201/09327 , H05K2201/09709 , H05K2201/09727 , H05K2201/10159
Abstract: A laminated wiring board includes a plurality of wiring layers that are stacked with the intermediary of an insulating layer between the layers and have a four-layer wiring unit obtained by disposing a power supply layer, a ground layer, a first signal wiring layer, and a second signal wiring layer sequentially from one side to the other side of a layer stacking direction with the intermediary of an insulating layer between the layers. One of the first signal wiring layer and the second signal wiring layer includes a data signal line and the other includes a clock signal line. The data signal line and the clock signal line are so disposed as to be prevented from overlapping with each other in a view perpendicular to the layer stacking direction at least at a place where both lines are disposed as parallel lines.
Abstract translation: 叠层布线板包括多个布线层，它们之间层叠有绝缘层，并且具有通过配置电源层，接地层，第一信号布线层和 第二信号布线层，顺序地从层叠层叠方向的一侧到另一侧，介于两层之间的绝缘层。 第一信号布线层和第二信号布线层中的一个包括数据信号线，另一个包括时钟信号线。 数据信号线和时钟信号线被布置成至少在两条线设置为平行线的地方，防止垂直于层叠方向的视线彼此重叠。
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Patent Agency Ranking
公开(公告)号：US08913401B2
公开(公告)日：2014-12-16
申请号：US13922349
申请日：2013-06-20
Applicant: Fuji Xerox Co., Ltd.
Inventor： Daisuke Iguchi
CPC classification number: H05K1/0243 , H05K1/0231 , H05K1/141 , H05K1/162 , H05K1/181 , H05K2201/041 , H05K2201/09309 , H05K2201/09327 , H05K2201/09345 , H05K2201/09663
Abstract: A multilayer wiring board includes a signal electrode, a first power supply electrode, and a ground electrode, which are connected to a first element that outputs a signal, an electrode connected to a second element that receives the signal, a ground layer that serves as a return path for a return current of the signal, a first power supply layer that is disposed adjacent to the ground layer with a dielectric layer interposed therebetween and supplies electric power to the first element, and a second power supply layer that is provided independently of the first power supply layer and supplies electric power to the second element. The first power supply layer causes the return current to return to the first element through the first power supply electrode as a displacement current between the ground layer and the first power supply layer.
Abstract translation: 多层布线板包括信号电极，第一电源电极和接地电极，它们连接到输出信号的第一元件，连接到接收信号的第二元件的电极，用作 用于所述信号的返回电流的返回路径，与所述接地层相邻设置有电介质层并且向所述第一元件提供电力的第一电源层和与所述第一电源层独立地设置的第二电源层， 第一电源层并且向第二元件供电。 第一电源层使返回电流通过第一电源电极返回到第一元件，作为接地层和第一电源层之间的位移电流。
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77.发明授权Multilayer circuit device having electrically isolated tightly spaced electrical current carrying traces 失效具有电隔离紧密间隔的电流携带痕迹的多层电路器件公开(公告)号：US08338712B2
公开(公告)日：2012-12-25
申请号：US12969478
申请日：2010-12-15
Applicant: Vinh T. Nguyen , Claude A. S. Hamrick
Inventor： Vinh T. Nguyen , Claude A. S. Hamrick
IPC: H05K1/00
CPC classification number: H05K3/1258 , H05K3/108 , H05K3/125 , H05K3/243 , H05K3/4611 , H05K3/4623 , H05K2201/09318 , H05K2201/09327 , H05K2201/09536 , H05K2201/098 , H05K2203/013 , H05K2203/0568 , Y10T29/49002 , Y10T29/49124 , Y10T29/49126 , Y10T29/49144 , Y10T29/49155 , Y10T29/49165
Abstract: A multilayer circuit device having electrically isolated tightly spaced electrical current carrying traces and including a first nonconductive substrate having a first conductive material affixed to a first side thereof to form a first ground plane, a plurality of elongated first conductive traces formed on a second side of the first non-conductive substrate and having transverse widths of 50 microns or less and rising above the upper surface of the first substrate to a height equal to or greater than the widths thereof such that a transverse cross section of the first conductive traces has a height-to-width ratio equal to or exceeding 1, adjacent ones of the first traces being separated from each other by first elongated spaces, the first conductive traces being variously useful as ground lines, signal lines and/or power lines.
Abstract translation: 一种具有电隔离紧密间隔的电流载流迹线并包括第一非导电基底的多层电路器件，所述第一非导电基底具有固定到其第一侧的第一导电材料以形成第一接地平面;多个细长的第一导电迹线，形成在第二侧 第一非导电衬底并且具有50微米或更小的横向宽度并且在第一衬底的上表面上方升高到等于或大于其宽度的高度，使得第一导电迹线的横截面具有高度 宽度比等于或超过1，相邻的第一迹线通过第一细长空间彼此分开，第一导电迹线在各种不同地用作接地线，信号线和/或电力线。
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公开(公告)号：US08326344B2
公开(公告)日：2012-12-04
申请号：US12520965
申请日：2007-12-27
Applicant: Shigeru Kemmochi , Keisuke Fukamachi , Kazuhiro Hagiwara
Inventor： Shigeru Kemmochi , Keisuke Fukamachi , Kazuhiro Hagiwara
CPC classification number: H04B1/44 , H01L2924/0002 , H05K1/0243 , H05K2201/093 , H05K2201/09327 , H05K2201/09781 , H01L2924/00
Abstract: A high-frequency device having high-frequency-signal-treating circuits in and on a laminate substrate comprising pluralities of dielectric layers having conductor patterns, the high-frequency-signal-treating circuits having amplifier circuits and switch circuits; terminals including input and output terminals of high-frequency signals, the power supply terminals of the amplifier circuits and the power supply terminals of the switch circuits being formed on one main surface of the laminate substrate; power supply lines each having one end connected to each of the power supply terminals of the amplifier circuits and power supply lines each having one end connected to each of the power supply terminals of the switch circuits being formed on one dielectric layer to constitute a power supply line layer; a first ground electrode being arranged on the side of the main surface with respect to the power supply line layer, the first ground electrode overlapping at least part of the power supply lines in a lamination direction; a second ground electrode being arranged on the opposite side of the first ground electrode with respect to the power supply line layer, the second ground electrode overlapping at least part of the power supply lines in a lamination direction; and the high-frequency-signal-treating circuits being arranged on the opposite side of the power supply line layer with respect to the second ground electrode.
Abstract translation: 一种具有高频信号处理电路的高频信号处理电路，包括具有导体图案的多个电介质层的层叠基板中及其上的高频信号处理电路，高频信号处理电路具有放大电路和开关电路; 包括高频信号的输入和输出端子的端子，放大器电路的电源端子和开关电路的电源端子形成在层叠基板的一个主表面上; 电源线各自具有连接到放大器电路的每个电源端子的一端和各自具有连接到开关电路的每个电源端子的一端的电源线，形成在一个电介质层上以构成电源 线层; 第一接地电极相对于电源线层布置在主表面侧，第一接地电极在层叠方向上与至少一部分电源线重叠; 第二接地电极相对于电源线层布置在第一接地电极的相对侧上，第二接地电极在层叠方向上与至少一部分电源线重叠; 并且高频信号处理电路相对于第二接地电极布置在电源线层的相对侧上。
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公开(公告)号：US20120201087A1
公开(公告)日：2012-08-09
申请号：US13349971
申请日：2012-01-13
Applicant: Satoshi Mizuno , Masafumi Oyama , Akira Arahata
Inventor： Satoshi Mizuno , Masafumi Oyama , Akira Arahata
CPC classification number: H05K1/0218 , H05K1/0228 , H05K1/025 , H05K2201/09327 , H05K2201/09709 , H05K2201/09727 , H05K2201/10159
Abstract: A laminated wiring board includes a plurality of wiring layers that are stacked with the intermediary of an insulating layer between the layers and have a four-layer wiring unit obtained by disposing a power supply layer, a ground layer, a first signal wiring layer, and a second signal wiring layer sequentially from one side to the other side of a layer stacking direction with the intermediary of an insulating layer between the layers. One of the first signal wiring layer and the second signal wiring layer includes a data signal line and the other includes a clock signal line. The data signal line and the clock signal line are so disposed as to be prevented from overlapping with each other in a view perpendicular to the layer stacking direction at least at a place where both lines are disposed as parallel lines.
Abstract translation: 叠层布线板包括多个布线层，它们之间层叠有绝缘层，并且具有通过配置电源层，接地层，第一信号布线层和 第二信号布线层，顺序地从层叠层叠方向的一侧到另一侧，介于两层之间的绝缘层。 第一信号布线层和第二信号布线层中的一个包括数据信号线，另一个包括时钟信号线。 数据信号线和时钟信号线被布置成至少在两条线设置为平行线的地方，防止垂直于层叠方向的视线彼此重叠。
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80.发明授权Substrate having a structure for suppressing noise generated in a power plane and/or a ground plane, and an electronic system including the same 有权具有用于抑制在电力平面和/或接地平面中产生的噪声的结构的基板，以及包括该基板的电子系统公开(公告)号：US08040201B2
公开(公告)日：2011-10-18
申请号：US12354488
申请日：2009-01-15
Applicant: Kwang-Soo Park , Byoung-Ha Oh , Yong-Ho Ko
Inventor： Kwang-Soo Park , Byoung-Ha Oh , Yong-Ho Ko
CPC classification number: H05K1/0216 , H05K1/0234 , H05K1/0298 , H05K1/09 , H05K1/167 , H05K2201/0338 , H05K2201/0352 , H05K2201/09318 , H05K2201/09327
Abstract: A substrate includes a power plane and a ground plane that are placed apart from and are substantially parallel to each other, and at least one signal line that is placed between the power plane and the ground plane. The ground plane includes a first conductive layer having a first conductivity. The power plane includes a second conductive layer having the first conductivity, and the power plane or the ground plane includes a third conductive layer having a second conductivity lower than the first conductivity. The third conductive layer faces the at least one signal line across a dielectric substance.
Abstract translation: 基板包括放置在彼此之间并且基本上彼此平行的电源平面和接地平面以及放置在电源平面和接地平面之间的至少一条信号线。 接地平面包括具有第一导电性的第一导电层。 功率平面包括具有第一导电性的第二导电层，并且功率平面或接地平面包括具有比第一导电率低的第二导电性的第三导电层。 第三导电层面对穿过电介质物质的至少一条信号线。
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