公开(公告)号：US20160181382A1

公开(公告)日：2016-06-23

申请号：US14577656

申请日：2014-12-19

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Didier Dutartre ,  David Barge

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/786 ,  H01L29/10

CPC classification number: H01L29/41783 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78618 ,  H01L29/78654

Abstract: A method for forming a transistor includes defining agate structure on a top surface of a first semiconductor layer of a silicon-on-insulator (SOI) substrate. The gate structure includes an insulating cover. A second semiconductor layer is then conformally deposited. The deposited second semiconductor layer includes an epitaxial portion on surfaces of the first semiconductor layer and an amorphous portion on surfaces of the insulating cover. The amorphous portion is then removed using a selective etch. The remaining epitaxial portion forms faceted raised source-drain structures on either side of the transistor gate structure. A slope of the sloped surface for the facet is dependent on the process parameters used during the conformal deposition.

Abstract translation: 一种用于形成晶体管的方法包括在绝缘体上硅（SOI）衬底的第一半导体层的顶表面上限定玛瑙结构。 门结构包括绝缘盖。 然后共形沉积第二半导体层。 沉积的第二半导体层包括在第一半导体层的表面上的外延部分和绝缘盖表面上的非晶部分。 然后使用选择性蚀刻除去非晶部分。 剩余的外延部分在晶体管栅极结构的任一侧上形成刻面凸起的源极 - 漏极结构。 用于小平面的倾斜表面的斜率取决于在保形沉积期间使用的工艺参数。

公开(公告)号：US09373714B2

公开(公告)日：2016-06-21

申请号：US14523996

申请日：2014-10-27

Applicant: STMicroelectronics SA

Inventor： Antoine Litty ,  Sylvie Ortolland

IPC: H01L29/78 ,  H01L29/786 ,  H01L27/12 ,  H01L29/10 ,  H03K17/687

CPC classification number: H01L29/7824 ,  H01L27/1203 ,  H01L29/1079 ,  H01L29/1087 ,  H01L29/78624 ,  H01L29/78648 ,  H03K17/687

Abstract: An extended-drain transistor is formed in a semiconductor layer arranged on one side of an insulating layer with a semiconductor region being arranged on the other side of the insulating layer. The semiconductor region includes a first portion of a first conductivity type arranged in front of the source and at least one larger portion of the gate and a second portion of a second conductivity type arranged in front of at least the larger portion of the extended drain region, each of the first and second portions being coupled to a connection pad.

Abstract translation: 延伸漏极晶体管形成在绝缘层的一侧上的半导体层中，半导体区域布置在绝缘层的另一侧上。 半导体区域包括布置在源极的前面的第一导电类型的第一部分和栅极的至少一个较大部分和布置在延伸漏极区域的至少较大部分的前面的第二导电类型的第二部分 所述第一和第二部分中的每一个耦合到连接垫。

公开(公告)号：US09331175B2

公开(公告)日：2016-05-03

申请号：US14452041

申请日：2014-08-05

Applicant: STMicroelectronics SA ,  STMicroelectronics, Inc.

Inventor： Pierre Morin ,  Denis Rideau ,  Olivier Nier

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324 ,  H01L21/762 ,  H01L29/78 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L29/66772 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/324 ,  H01L21/76283 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7847

Abstract: The disclosure concerns a method of stressing a semiconductor layer comprising: depositing, over a semiconductor on insulator (SOI) structure having a semiconductor layer in contact with an insulating layer, a stress layer; locally stressing said semiconductor layer by forming one or more openings in said stress layer, said openings being aligned with first regions of said semiconductor layer in which transistor channels are to be formed; and deforming second regions of said insulating layer adjacent to said first regions by temporally decreasing, by annealing, the viscosity of said insulator layer.

Abstract translation: 本公开涉及一种应力半导体层的方法，包括：在绝缘体上半导体层（SOI）结构上沉积，该结构具有与绝缘层接触的半导体层，应力层; 通过在所述应力层中形成一个或多个开口来对所述半导体层进行局部应力，所述开口与要形成晶体管沟道的所述半导体层的第一区对齐; 以及通过退火所述绝缘体层的粘度暂时减小所述绝缘层的与所述第一区域相邻的第二区域。

公开(公告)号：US20160118953A1

公开(公告)日：2016-04-28

申请号：US14981189

申请日：2015-12-28

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Frederic Gianesello ,  Romain Pilard ,  Cedric Durand

IPC: H03H7/42 ,  H04W88/02 ,  H01F27/40 ,  H01F27/28 ,  H01F27/29

CPC classification number: H03H7/42 ,  H01F27/2804 ,  H01F27/29 ,  H01F27/38 ,  H01F27/40 ,  H01L23/5223 ,  H01L23/5227 ,  H01L2924/0002 ,  H04W88/02 ,  Y10T29/4902 ,  H01L2924/00

Abstract: A transformer of the balanced-unbalanced type includes a primary inductive circuit and a secondary inductive circuit housed inside an additional inductive winding connected in parallel to the terminals of the secondary circuit and inductively coupled with the primary circuit and the secondary circuit.

公开(公告)号：US09324612B2

公开(公告)日：2016-04-26

申请号：US13899326

申请日：2013-05-21

Applicant: STMicroelectronics SA

Inventor： Sylvain Joblot ,  Pierre Bar

IPC: H01L23/48 ,  H01L23/52 ,  H01L21/768 ,  H01P3/00 ,  H01P11/00

CPC classification number: H01L21/76898 ,  H01L21/76831 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/5329 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01P3/003 ,  H01P3/006 ,  H01P11/003 ,  H01L2924/00

Abstract: In one embodiment there is disclosed a method for manufacturing an integrated circuit in a semiconductor substrate including through vias and a coplanar line, including the steps of: forming active components and a set of front metallization levels; simultaneously etching from the rear surface of the substrate a through via hole and a trench crossing the substrate through at least 50% of its height; coating with a conductive material the walls and the bottom of the hole and of the trench; and filling the hole and the trench with an insulating filling material; and forming a coplanar line extending on the rear surface of the substrate, in front of the trench and parallel thereto, so that the lateral conductors of the coplanar line are electrically connected to the conductive material coating the walls of the trench.

Abstract translation: 在一个实施例中，公开了一种用于在包括通孔和共面线的半导体衬底中制造集成电路的方法，包括以下步骤：形成有源部件和一组前金属化层; 同时从衬底a的后表面通过通孔和穿过衬底穿过其高度的至少50％的沟槽; 用导电材料涂覆壁和孔的底部和沟槽; 并用绝缘填充材料填充孔和沟槽; 并且在沟槽的前面并与其平行地形成在衬底的后表面上延伸的共面线，使得共面线的横向导体电连接到涂覆沟槽的壁的导电材料。

公开(公告)号：US20160109732A1

公开(公告)日：2016-04-21

申请号：US14981139

申请日：2015-12-28

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Jean-Robert Manouvrier ,  Frederic Boeuf

IPC: G02F1/025

CPC classification number: G02F1/025 ,  G02F1/225 ,  G02F2001/212

Abstract: An electro-optical phase shifter to be located in an optical waveguide may include a rib of a semiconductor material extending along a length of the optical waveguide and a control structure configured to modify a concentration of carriers in the rib according to a control voltage present between first and second control terminals of the phase shifter. The control structure may include a conductive layer covering a portion of the rib and electrically connected to a first of the control terminals. An insulating layer may be configured to electrically isolate the conductive layer from the rib.

Abstract translation: 位于光波导中的电光移相器可以包括沿着光波导的长度延伸的半导体材料的肋，以及控制结构，其被配置为根据存在于所述肋之间的控制电压来修改肋中的载流子的浓度 移相器的第一和第二控制端子。 控制结构可以包括覆盖肋的一部分并电连接到第一控制端的导电层。 绝缘层可以被配置为将导电层与肋电隔离。

公开(公告)号：US20160097898A1

公开(公告)日：2016-04-07

申请号：US14970792

申请日：2015-12-16

Applicant: STMicroelectronics SA

Inventor： Sylvain Joblot ,  Pierre Bar

IPC: G02B6/12 ,  H01L21/48 ,  H01L21/768

CPC classification number: H01L21/76831 ,  G02B6/12 ,  H01L21/4846 ,  H01L21/76224 ,  H01L21/76898 ,  H01L23/66 ,  H01P11/003

Abstract: An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via.

Abstract translation: 集成电路包括绝缘体上硅晶片和互连层，其为在支撑体的顶侧上方形成的共面波导提供支撑。 穿通硅通孔由支撑体的背面形成并穿过绝缘体上硅晶片以到达互连层。 从共面波导下方的支撑体的背面形成沟槽。 沟槽在共面波导的至少整个长度上延伸。 沟槽穿过绝缘体上硅晶片以到达互连层，并且可以具有与穿硅通孔基本相同的深度。

公开(公告)号：US20160079388A1

公开(公告)日：2016-03-17

申请号：US14855834

申请日：2015-09-16

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Christian ARVET ,  Sébastien BARNOLA ,  Sébastien LAGRASTA ,  Nicolas POSSEME

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/51 ,  H01L21/283 ,  H01L21/311

CPC classification number: H01L29/6656 ,  H01L21/02326 ,  H01L21/0234 ,  H01L21/283 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/42364 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66628

Abstract: The production of spacers at flanks of a transistor gate, including a step of forming a dielectric layer covering the gate and a peripheral region of a layer of semiconductor material surrounding the gate, including forming a superficial layer covering the gate and the peripheral region; partially removing the superficial layer configured so as to completely remove the superficial layer at the peripheral region while preserving a residual part of the superficial layer at the flanks; and selective etching of the dielectric layer vis-à-vis the material of the residual part of the superficial layer and vis-à-vis the semiconductor material.

Abstract translation: 在晶体管栅极的侧面制造间隔物，包括形成覆盖栅极的介电层和围绕栅极的半导体材料层的外围区域的步骤，包括形成覆盖栅极和外围区域的表面层; 部分去除表层，构造成在外围区域完全除去表层，同时在侧面保留表层的残留部分; 并且相对于表层的残余部分的材料和相对于半导体材料的材料的电介质层的选择性蚀刻。

公开(公告)号：US20160049992A1

公开(公告)日：2016-02-18

申请号：US14821053

申请日：2015-08-07

Applicant: STMicroelectronics SA

Inventor： Philippe Galy

IPC: H04B3/54 ,  H04L7/033

CPC classification number: H04B3/548 ,  H03M9/00 ,  H04L7/033 ,  H04L25/4917

Abstract: A data transmission circuit transmits a data signal over a transmission line. A digital to analog converter (DAC) operates to receive N-bit input digital values for conversion to corresponding ones of 2N different DC voltage levels. The DAC selects, for each N-bit input digital value, one of the 2N DC voltage levels. An analog to digital converter (ADC) operates to sense the DC voltage on the transmission line for conversion to a corresponding N-bit output digital value.

Abstract translation: 数据传输电路通过传输线传输数据信号。 数模转换器（DAC）用于接收N位输入数字值，以转换为2N个不同直流电压电平中的相应的数字值。 DAC为每个N位输入数字值选择2N直流电压电平之一。 模数转换器（ADC）用于检测传输线上的直流电压，以转换为相应的N位输出数字值。

公开(公告)号：US09240325B2

公开(公告)日：2016-01-19

申请号：US14498091

申请日：2014-09-26

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (Crolles 2) SAS

Inventor： Sébastien Barnola ,  Yves Morand ,  Heimanu Niebojewski

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/283 ,  H01L29/66 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L29/42372 ,  H01L21/28008 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/283 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/45 ,  H01L29/49 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66507 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78

Abstract: A method includes making a gate stack on the surface of an active zone, including depositing a first dielectric layer; depositing a gate conductive layer; depositing a first metal layer; depositing a second metal layer; depositing a second dielectric layer; partially etching the gate stack for the formation of a gate zone on the active zone; making insulating spacers on either side of the gate zone on the active zone; making source and drain electrodes zones; making silicidation zones on the surface of the source and drain zones; etching, in the gate zone on the active zone, the second dielectric layer and the second metal layer with stopping on the first metal layer, so as to form a cavity between the insulating spacers; making a protective plug at the surface of the first metal layer of the gate zone on the active zone, where the protective plug fills the cavity.

Abstract translation: 一种方法包括在有源区的表面上形成栅极堆叠，包括沉积第一介电层; 沉积栅极导电层; 沉积第一金属层; 沉积第二金属层; 沉积第二电介质层; 部分地蚀刻栅极堆叠以在有源区上形成栅极区; 在活动区域​​上的栅极区域的任一侧上制造绝缘垫片; 制造源极和漏极区域; 在源极和漏极区域的表面上形成硅化物区域; 在活性区域的栅极区域中蚀刻在第一金属层上停止的第二介电层和第二金属层，以在绝缘间隔物之间​​形成空腔; 在活动区域​​上的栅极区域的第一金属层的表面上形成保护塞，其中保护塞填充空腔。