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103 条记录 (耗时 0.02 秒)

    Programmable impedance control circuit and method thereof
    81.
    发明授权
    Programmable impedance control circuit and method thereof 有权
    可编程阻抗控制电路及其方法

    公开(公告)号：US06429679B1

    公开(公告)日：2002-08-06

    申请号：US09853101

    申请日：2001-05-10

    申请人： Nam-Seog Kim ,  Uk-Rae Cho

    发明人： Nam-Seog Kim ,  Uk-Rae Cho

    IPC分类号： H03K19003

    CPC分类号： H03K19/0005

    摘要： A programmable impedance control circuit for detecting a characteristic impedance of transmission line to thereby output it to an output driver and on-chip terminator in a semiconductor device. Particularly the circuit serves to control an internal impedance according to a controlled, programmable protocol irrespective of the changes in an external impedance due to factors such as voltage and temperature after an initial internal impedance is set during a locking operation.

    摘要翻译： 一种用于检测传输线的特性阻抗从而将其输出到半导体器件中的输出驱动器和片上终端器的可编程阻抗控制电路。 特别地，电路用于根据受控的可编程协议来控制内部阻抗，而不管由于在锁定操作期间设置初始内部阻抗之后诸如电压和温度等因素导致的外部阻抗的变化。

    Semiconductor memory device with hierarchical bit line structure
    87.
    发明授权
    Semiconductor memory device with hierarchical bit line structure 有权

    公开(公告)号：US07616512B2

    公开(公告)日：2009-11-10

    申请号：US12347233

    申请日：2008-12-31

    申请人： Nam-Seog Kim ,  Jong-Cheol Lee ,  Hak-Soo Yu ,  Uk-Rae Cho

    发明人： Nam-Seog Kim ,  Jong-Cheol Lee ,  Hak-Soo Yu ,  Uk-Rae Cho

    IPC分类号： G11C7/00

    CPC分类号： G11C11/417 ,  G11C7/18 ,  G11C8/12

    摘要： A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.

    Semiconductor device packages and methods of fabricating the same
    88.
    发明申请
    Semiconductor device packages and methods of fabricating the same 审中-公开
    半导体器件封装及其制造方法

    公开(公告)号：US20090186446A1

    公开(公告)日：2009-07-23

    申请号：US12313980

    申请日：2008-11-26

    申请人： Yong-Chai Kwon ,  Nam-Seog Kim ,  Keum-Hee Ma ,  Ho-Jin Lee

    发明人： Yong-Chai Kwon ,  Nam-Seog Kim ,  Keum-Hee Ma ,  Ho-Jin Lee

    IPC分类号： H01L21/50

    CPC分类号： H01L23/3128 ,  H01L23/055 ,  H01L23/10 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/97 ,  H01L2225/06572 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2224/81 ,  H01L2924/00

    摘要： Provided are semiconductor device packages and methods for fabricating the same. In some embodiments, the method includes providing a semiconductor chip on a substrate with through electrodes formed in the substrate, and providing a capping layer on the substrate to receive the semiconductor chip in a recess formed in the capping layer. The capping layer is coupled to the substrate by a bonding layer formed on the substrate, and the capping layer covers the semiconductor chip provided on the substrate. The processing of the substrate and the capping layer can be separately performed, thus allowing the material for the capping layer and/or the substrate to be selected to reduce (e.g., to minimize) a difference between the thermal expansion coefficients of the capping layer material and the substrate material.

    摘要翻译： 提供半导体器件封装及其制造方法。 在一些实施例中，该方法包括在基板上提供半导体芯片，该基板上形成有贯通电极，并在基板上提供覆盖层，以将半导体芯片接收在形成于封盖层中的凹槽中。 覆盖层通过形成在基板上的接合层耦合到基板，并且覆盖层覆盖设置在基板上的半导体芯片。 衬底和封盖层的处理可以分别进行，从而允许选择覆盖层和/或衬底的材料以减小（例如，最小化）封盖层材料的热膨胀系数之间的差异 和基材。

    SEMICONDUCTOR MEMORY DEVICE WITH HIERARCHICAL BIT LINE STRUCTURE
    89.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE WITH HIERARCHICAL BIT LINE STRUCTURE 有权
    具有分层位线结构的半导体存储器件

    公开(公告)号：US20090154265A1

    公开(公告)日：2009-06-18

    申请号：US12347239

    申请日：2008-12-31

    申请人： Nam-Seog KIM ,  Jong-Cheol LEE ,  Hak-Soo YU ,  Uk-Rae CHO

    发明人： Nam-Seog KIM ,  Jong-Cheol LEE ,  Hak-Soo YU ,  Uk-Rae CHO

    IPC分类号： G11C11/416 ,  G11C8/00

    CPC分类号： G11C11/417 ,  G11C7/18 ,  G11C8/12

    摘要： A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.

    摘要翻译： 半导体存储器件具有分层位线结构。 半导体存储器件可以包括第一和第二存储器单元簇，其共享相同的位线对并且在操作上被分割; 第三和第四存储单元簇，其分别对应于与第一和第二存储器单元簇耦合的字线，并且共享与位线对不同的位线对，并在操作上分割; 以及用于响应于列选择信号将与第一至第四存储器单元簇连接的位线对之一切换到公共读出放大器的列通路。 由此，连接到位线的外围电路的负载导致的工作速度降低得到改善，并且随着芯片尺寸的减小，列通道的数量大幅减少。