公开(公告)号：US11901287B2

公开(公告)日：2024-02-13

申请号：US17476344

申请日：2021-09-15

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Lifang Xu

IPC: H01L23/522 ,  H01L21/768 ,  H10B69/00

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H10B69/00

Abstract: Microelectronic devices include a stack structure having a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one stadium, of stadiums within the stack structure, comprise staircase(s) having steps provided by a group of the conductive structures. Step contacts extend to the steps of the staircase(s) of the at least one of the stadiums. Each conductive structure of the group of conductive structures has more than one of the step contacts in contact therewith at at least one of the steps of the staircase(s). Additional microelectronic devices are also disclosed, as are methods of fabrication and electronic systems.

公开(公告)号：US20240029794A1

公开(公告)日：2024-01-25

申请号：US17868118

申请日：2022-07-19

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Anna Maria Conti ,  Harsh Narendrakumar Jain ,  H. Montgomery Manning

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11582

CPC classification number: G11C16/0483 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565 ,  H01L27/11582

Abstract: A method used in forming memory circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack extends from a memory-array region into a stair-step region. The first tiers are conductive and the second tiers are insulative at least in a finished-circuitry construction. A first layer of imageable resist is exposed to actinic radiation and developed to form a first opening there-through in the stair-step region. The developed first layer is used in a plurality of alternating etching and lateral-trimming steps that widens the first opening and forms two opposing flights of stairs in the stack in the stair-step region. A second layer of imageable resist is formed directly above the two opposing flights of stairs. The second layer is exposed to actinic radiation and developed to form a second opening there-through. The second opening exposes all of the stairs of one of the two opposing flights. The second layer is directly above all of the stairs in the other of the two opposing flights. The developed second layer is used in a plurality of alternating etching and lateral-trimming steps that widens the second opening, lengthens at least one of the two opposing flights of stairs, and extends the two opposing flights of stairs deeper into the stack. Other embodiments, including structure, are disclosed.

公开(公告)号：US20230387353A1

公开(公告)日：2023-11-30

申请号：US18359795

申请日：2023-07-26

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Scott D. Schellhammer ,  Shan Ming Mou ,  Michael J. Bernhardt

IPC: H01L33/38 ,  H01L31/0216 ,  H01L33/22 ,  H01L31/0236 ,  H01L33/42 ,  H01L33/58

CPC classification number: H01L33/38 ,  H01L31/02168 ,  H01L33/22 ,  H01L31/0236 ,  H01L33/42 ,  H01L33/58 ,  H01L2933/0091 ,  Y02E10/50

Abstract: Textured optoelectronic devices and associated methods of manufacture are disclosed herein. In several embodiments, a method of manufacturing a solid state optoelectronic device can include forming a conductive transparent texturing material on a substrate. The method can further include forming a transparent conductive material on the texturing material. Upon heating the device, the texturing material causes the conductive material to grow a plurality of protuberances. The protuberances can improve current spreading and light extraction from the device.

公开(公告)号：US11805653B2

公开(公告)日：2023-10-31

申请号：US17145131

申请日：2021-01-08

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Kamal M. Karda ,  Gurtej S. Sandhu ,  Sanh D. Tang ,  Akira Goda ,  Lifang Xu

IPC: H01L27/11573 ,  H10B43/40 ,  G11C16/08 ,  H01L23/532 ,  H01L21/28 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

CPC classification number: H10B43/40 ,  G11C16/08 ,  H01L23/5329 ,  H01L29/40117 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40

Abstract: A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.

公开(公告)号：US20230301081A1

公开(公告)日：2023-09-21

申请号：US18321659

申请日：2023-05-22

Applicant: Micron Technology, Inc.

Inventor： Christopher J. Larsen ,  Lifang Xu

IPC: H10B41/27 ,  H01L21/768 ,  H01L23/538 ,  G11C5/06 ,  H10B43/27

CPC classification number: H10B41/27 ,  H01L21/76877 ,  H01L23/5384 ,  H01L23/5386 ,  G11C5/06 ,  H01L23/5381 ,  H10B43/27

Abstract: A microelectronic device comprises a stack structure comprising blocks separated from one another by dielectric slot structures. At least one of the blocks comprises two crest regions, a stadium structure interposed between the two crest regions in a first horizontal direction, and two bridge regions neighboring opposing sides of the stadium structure in a second horizontal direction. A filled trench vertically overlies and is within horizontal boundaries of the stadium structure of the at least one of the blocks. The filled trench comprises a dielectric liner material on the opposing staircase structures of the stadium structure and on inner sidewalls of the two bridge regions, and dielectric structures on and having a different material composition than the dielectric liner material. The dielectric structures are substantially confined within horizontal areas of the steps of the stadium structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US11690234B2

公开(公告)日：2023-06-27

申请号：US17652346

申请日：2022-02-24

Applicant: Micron Technology, Inc.

Inventor： Bo Zhao ,  Nancy M. Lomeli ,  Lifang Xu ,  Adam L. Olson

IPC: H01L27/00 ,  H01L21/8229 ,  H01L21/768 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11578

CPC classification number: H01L21/8229 ,  H01L21/76822 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578 ,  H01L21/76877

Abstract: A microelectronic device comprises a microelectronic device structure having a memory array region and a staircase region. The microelectronic device structure comprises a stack structure having tiers each comprising a conductive structure and an insulative structure; staircase structures confined within the staircase region and having steps comprising edges of the tiers of the stack structure within the deck and the additional deck; and semiconductive pillar structures confined within the memory array region and extending through the stack structures. The stack structure comprises a deck comprising a group of the tiers; an additional deck overlying the deck and comprising an additional group of the tiers; and an interdeck section between the deck and the additional deck and comprising a dielectric structure confined within the memory array region, and another group of the tiers within vertical boundaries of the dielectric structure and confined within the staircase region.

公开(公告)号：US11670738B2

公开(公告)日：2023-06-06

申请号：US16784879

申请日：2020-02-07

Applicant: Micron Technology, Inc.

Inventor： Martin F. Schubert ,  Vladimir Odnoblyudov ,  Lifang Xu

IPC: H01L33/38 ,  H01L33/60 ,  H01L33/42 ,  H01L33/00 ,  H01L33/40 ,  H01L33/06 ,  H01L33/32 ,  H01L33/50 ,  H01L33/56 ,  H01L33/30

CPC classification number: H01L33/382 ,  H01L33/0093 ,  H01L33/0095 ,  H01L33/06 ,  H01L33/30 ,  H01L33/32 ,  H01L33/405 ,  H01L33/42 ,  H01L33/502 ,  H01L33/56 ,  H01L2933/0016

Abstract: Solid-state radiation transducer (SSRT) devices having buried contacts that are at least partially transparent and associated systems and methods are disclosed herein. An SSRT device configured in accordance with a particular embodiment can include a radiation transducer including a first semiconductor material, a second semiconductor material, and an active region between the first semiconductor material and the second semiconductor material. The SSRT device can further include first and second contacts electrically coupled to the first and second semiconductor materials, respectively. The second contact can include a plurality of buried-contact elements electrically coupled to the second semiconductor material. Individual buried-contact elements can have a transparent portion directly adjacent to the second semiconductor material. The second contact can further include a base portion extending between the buried-contact elements, such as a base portion that is least partially planar and reflective.

公开(公告)号：US20230065142A1

公开(公告)日：2023-03-02

申请号：US17968651

申请日：2022-10-18

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  Paolo Tessariol ,  David H. Wells ,  Lars P. Heineck ,  Richard J. Hill ,  Lifang Xu ,  Indra V. Chary ,  Emilio Camerlenghi

IPC: G11C5/06 ,  H01L21/50 ,  H01L27/11582 ,  H01L27/11556 ,  H01L25/065

Abstract: Some embodiments include an integrated assembly having a pair of adjacent memory-block-regions, and having a separator structure between the adjacent memory-block-regions. The memory-block-regions include a first stack of alternating conductive levels and first insulative levels. The separator structure includes a second stack of alternating second and third insulative levels. The second insulative levels are substantially horizontally aligned with the conductive levels, and the third insulative levels are substantially horizontally aligned with the first insulative levels. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11514953B2

公开(公告)日：2022-11-29

申请号：US17243937

申请日：2021-04-29

Applicant: Micron Technology, Inc.

Inventor： Yoshiaki Fukuzumi ,  Paolo Tessariol ,  David H. Wells ,  Lars P. Heineck ,  Richard J. Hill ,  Lifang Xu ,  Indra V. Chary ,  Emilio Camerlenghi

IPC: G11C11/34 ,  G11C5/06 ,  H01L21/50 ,  H01L27/11582 ,  H01L27/11556 ,  H01L25/065

Abstract: Some embodiments include an integrated assembly having a pair of adjacent memory-block-regions, and having a separator structure between the adjacent memory-block-regions. The memory-block-regions include a first stack of alternating conductive levels and first insulative levels. The separator structure includes a second stack of alternating second and third insulative levels. The second insulative levels are substantially horizontally aligned with the conductive levels, and the third insulative levels are substantially horizontally aligned with the first insulative levels. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20220238444A1

公开(公告)日：2022-07-28

申请号：US17658907

申请日：2022-04-12

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  Rita J. Klein ,  Everett A. McTeer ,  Lifang Xu ,  Daniel Billingsley ,  Collin Howder

IPC: H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522

Abstract: A microelectronic device includes a stack structure, a staircase structure, conductive pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulating structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulating structures. The staircase structure has steps made up of edges of at least some of the tiers of the stack structure. The conductive pad structures are on the steps of the staircase structure and include beta phase tungsten. The conductive contact structures are on the conductive pad structures. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.