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177 条记录 (耗时 0.026 秒)

    OPTIMIZED ANNULAR COPPER TSV
    81.
    发明申请
    OPTIMIZED ANNULAR COPPER TSV 有权
    优化的环形铜片TSV

    公开(公告)号：US20120326309A1

    公开(公告)日：2012-12-27

    申请号：US13167107

    申请日：2011-06-23

    申请人： PAUL S ANDRY ,  Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Emily R. Kinser ,  Cornelia K. Tsang ,  Richard P. Volant

    发明人： PAUL S ANDRY ,  Mukta G. Farooq ,  Robert Hannon ,  Subramanian S. Iyer ,  Emily R. Kinser ,  Cornelia K. Tsang ,  Richard P. Volant

    IPC分类号： H01L23/48 ,  H01L21/283

    CPC分类号： H01L21/76846 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.

    摘要翻译： 本公开提供了热机械可靠的铜TSV和在BEOL处理期间形成这种TSV的技术。 TSV构成延伸穿过半导体衬底的环形沟槽。 衬底限定沟槽的内侧壁和外侧壁，该侧壁分隔5至10微米的距离。 包括铜或铜合金的导电路径从所述第一介电层的上表面通过所述衬底在所述沟槽内延伸。 基板厚度可以为60微米或更小。 具有导电连接到导电路径的互连金属化的电介质层直接形成在所述环形沟槽上。

    CIRCUIT DESIGN CHECKING FOR THREE DIMENSIONAL CHIP TECHNOLOGY
    82.
    发明申请
    CIRCUIT DESIGN CHECKING FOR THREE DIMENSIONAL CHIP TECHNOLOGY 有权
    电路设计检查三维芯片技术

    公开(公告)号：US20120304138A1

    公开(公告)日：2012-11-29

    申请号：US13113421

    申请日：2011-05-23

    申请人： Mukta G. Farooq ,  John A. Griesemer ,  William Francis Landers ,  Kevin S. Petrarca ,  Richard Paul Volant

    发明人： Mukta G. Farooq ,  John A. Griesemer ,  William Francis Landers ,  Kevin S. Petrarca ,  Richard Paul Volant

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081

    摘要： A tool that allows three dimensional chip circuit designs to be checked subsequent to 3D design layer mirroring. The 3D chip design is converted to a corresponding 2D chip design by mirroring one or more design layers from the mirrored side of a 3D design and merging those design layers with unmirrored design layers from the unmirrored side of a 3D design. The converted circuit design can be processed by standard verification checks. The tool may also receive design layers corresponding to an integrated circuit that will pass through multiple semiconductor chips. Each design cell is examined to determine if it corresponds to a mirrored or unmirrored side of its respective semiconductor chip. If the respective design cell corresponds to the mirrored side, the design cell is mirrored. All mirrored cells are then merged with the unmirrored design cells in the correct order. The merged design is processed by standard verification checks. The tool also has the capability to create terminal metal abstracts for two adjoining chips. One of the abstracts is mirrored and then merged with the other for connectivity and alignment checking.

    摘要翻译： 一种允许在3D设计层镜像之后检查三维芯片电路设计的工具。 通过从3D设计的镜像侧镜像一个或多个设计层，将3D芯片设计转换为相应的2D芯片设计，并将这些设计层与未设计的设计层从3D设计的非镜面合并。 转换电路设计可以通过标准验证检查进行处理。 该工具还可以接收对应于将通过多个半导体芯片的集成电路的设计层。 检查每个设计单元以确定它是否对应于其相应的半导体芯片的镜像或非镜像侧。 如果相应的设计单元对应于镜像侧，则设计单元被镜像。 然后所有镜像单元格以正确的顺序与未设计的设计单元合并。 合并设计通过标准验证检查进行处理。 该工具还可以为两个相邻的芯片创建终端金属摘要。 其中一个摘要被镜像，然后与另一个摘要进行连接和对齐检查。

    3-D Integration using Multi Stage Vias
    83.
    发明申请
    3-D Integration using Multi Stage Vias 有权
    使用多级通道的3-D集成

    公开(公告)号：US20120280395A1

    公开(公告)日：2012-11-08

    申请号：US13101268

    申请日：2011-05-05

    申请人： Mukta G. Farooq ,  Troy L. Graves-Abe

    发明人： Mukta G. Farooq ,  Troy L. Graves-Abe

    IPC分类号： H01L23/48 ,  H01L21/3205

    CPC分类号： H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A TSV can be formed having a top section via formed through the top substrate surface and a bottom section via formed through the bottom substrate surface. The top section cross section can have a minimum cross section corresponding to design rules, and the top section depth can correspond to a workable aspect ratio. The top section via can be filled or plugged so that top side processing can be continued. The bottom section via can have a larger cross section for ease of forming a conductive path therethrough. The bottom section via extends from the back side to the bottom of the top section via and is formed after the substrate has been thinned. The TSV is can be completed by forming a conductive path after removing sacrificial fill materials from the joined top and bottom section vias.

    摘要翻译： 可以形成TSV，其具有通过顶部衬底表面形成的顶部截面，以及通过底部衬底表面形成的底部截面。 顶部截面可以具有对应于设计规则的最小横截面，并且顶部截面深度可对应于可工作的纵横比。 顶部通孔可以被填充或插入，以便可以继续顶部处理。 底部通孔可以具有更大的横截面，以便于形成穿过其中的导电路径。 底部部分通孔从顶部部分通孔的背面延伸到底部，并且在基板变薄之后形成。 可以通过在从接合的顶部和底部部分通孔去除牺牲填充材料之后形成导电路径来完成TSV。

    Coaxial through-silicon via
    84.
    发明授权
    Coaxial through-silicon via 有权
    同轴穿硅通孔

    公开(公告)号：US08242604B2

    公开(公告)日：2012-08-14

    申请号：US12607098

    申请日：2009-10-28

    申请人： Richard P. Volant ,  Mukta G. Farooq ,  Paul F. Findeis ,  Kevin S. Petrarca

    发明人： Richard P. Volant ,  Mukta G. Farooq ,  Paul F. Findeis ,  Kevin S. Petrarca

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A through-silicon via (TSV) structure forming a unique coaxial or triaxial interconnect within the silicon substrate. The TSV structure is provided with two or more independent electrical conductors insulated from another and from the substrate. The electrical conductors can be connected to different voltages or ground, making it possible to operate the TSV structure as a coaxial or triaxial device. Multiple layers using various insulator materials can be used as insulator, wherein the layers are selected based on dielectric properties, fill properties, interfacial adhesion, CTE match, and the like. The TSV structure overcomes defects in the outer insulation layer that may lead to leakage. A method of fabricating such a TSV structure is also described.

    摘要翻译： 硅通孔（TSV）结构在硅衬底内形成独特的同轴或三轴互连。 TSV结构设置有两个或更多个与另一个绝缘的独立电导体和与衬底绝缘的独立电导体。 电导体可以连接到不同的电压或接地，使得可以将TSV结构作为同轴或三轴装置进行操作。 使用各种绝缘材料的多层可用作绝缘体，其中根据介电性能，填充性能，界面粘合性，CTE匹配等来选择层。 TSV结构克服了外绝缘层中可能导致泄漏的缺陷。 还描述了制造这种TSV结构的方法。

    Three Dimensional Integration and Methods of Through Silicon Via Creation
    85.
    发明申请
    Three Dimensional Integration and Methods of Through Silicon Via Creation 失效
    通过创建硅通过三维集成和方法

    公开(公告)号：US20120190189A1

    公开(公告)日：2012-07-26

    申请号：US13422415

    申请日：2012-03-16

    申请人： Mukta G. Farooq ,  Emily R. Kinser ,  Richard Wise ,  Hakeem Yusuff

    发明人： Mukta G. Farooq ,  Emily R. Kinser ,  Richard Wise ,  Hakeem Yusuff

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76847 ,  H01L21/0337 ,  H01L21/32136 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

    摘要： A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a sacrificial substrate layer, etching to the exposed first planar area to form a cavity having a first depth in the structure, removing a portion of the photoresist to increase the size of the opening to define a second planar area on the sacrificial substrate layer, forming a doped portion in the sacrificial substrate layer, and etching the cavity to increase the depth of the cavity to expose a first conductor in the structure and to increase the planar area and depth of a portion of the cavity to expose a second conductor in the structure.

    摘要翻译： 一种方法包括在结构上图案化光致抗蚀剂层以限定开口并暴露牺牲衬底层上的第一平面区域，蚀刻到暴露的第一平面区域以形成具有在结构中的第一深度的空腔， 光致抗蚀剂以增加开口的尺寸以在牺牲衬底层上限定第二平面区域，在牺牲衬底层中形成掺杂部分，以及蚀刻空腔以增加空腔的深度以暴露结构中的第一导体，以及 以增加空腔的一部分的平面面积和深度以暴露结构中的第二导体。