公开(公告)号：US20070152325A1

公开(公告)日：2007-07-05

申请号：US11323243

申请日：2005-12-30

申请人： Ashay Dani ,  Anna Prakash ,  Saikumar Jayaraman ,  Mitesh Patel ,  Vijay Wakharkar

发明人： Ashay Dani ,  Anna Prakash ,  Saikumar Jayaraman ,  Mitesh Patel ,  Vijay Wakharkar

IPC分类号： H01L23/34 ,  H01L21/48

CPC分类号： H01L23/42 ,  H01L23/3731 ,  H01L23/3732 ,  H01L23/3737 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/04941 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/00 ,  H01L2224/05599

摘要： A chip package includes a thermal interface material disposed between a die backside and a heat sink. A dielectric sheet is also disposed between the die backside and the heat sink. The dielectric sheet diminishes overall heat transfer from the die to the heat sink by a small fraction of total possible heat transfer without the dielectric sheet. A method of operating the chip includes biasing the chip with the dielectric sheet in place.

摘要翻译： 芯片封装包括设置在模具背面和散热器之间的热界面材料。 电介质片也设置在模具背面和散热器之间。 电介质薄片通过少量的总可能的热传递而减少了从模具到散热器的总传热，而没有电介质片材。 操作芯片的方法包括将电介质片偏置在适当位置。

公开(公告)号：US20070148360A1

公开(公告)日：2007-06-28

申请号：US11684739

申请日：2007-03-12

申请人： Terry Sterrett ,  Tian-An Chen ,  Saikumar Jayaraman

发明人： Terry Sterrett ,  Tian-An Chen ,  Saikumar Jayaraman

IPC分类号： B05D7/00

CPC分类号： C08L101/12 ,  B29C39/026 ,  B29C70/58 ,  B29C70/882 ,  B29L2031/3406 ,  C08J5/10 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/30107 ,  H05K3/321 ,  H05K2201/0367 ,  H05K2201/10674 ,  H05K2201/10719 ,  Y10T428/24917 ,  Y10T428/25 ,  Y10T428/31681 ,  H01L2924/00 ,  H01L2224/0401

摘要： A method for low temperature bumping is disclosed. A resin capable of being cross-linked by free-radical or cationic polymerization at low temperature is provided. Electrically conductive particles are then added to the resin to form a mixture. The mixture is then activated by heat or exposure to light to polymerize the mixture. In an alternative embodiment, a vinyl ether resin is used, to which electrically conductive particles are added. The mixture is polymerized by exposure to light.

摘要翻译： 公开了一种低温碰撞的方法。 提供能够在低温下通过自由基或阳离子聚合交联的树脂。 然后将导电颗粒加入到树脂中以形成混合物。 然后通过加热或暴露于光使混合物活化，以使混合物聚合。 在替代实施方案中，使用乙烯基醚树脂，其中加入导电颗粒。 混合物通过曝光聚合。

公开(公告)号：US07183139B2

公开(公告)日：2007-02-27

申请号：US10794467

申请日：2004-03-04

申请人： Saikumar Jayaraman ,  Vijay S. Wakharkar

发明人： Saikumar Jayaraman ,  Vijay S. Wakharkar

IPC分类号： H01L21/44

CPC分类号： H01L23/293 ,  C08G59/3254 ,  H01L21/563 ,  H01L24/29 ,  H01L24/743 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/92125 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/13111 ,  H01L2924/0665 ,  H01L2224/0401

摘要： A system for underfilling in a chip package includes an underfill mixture that ameliorates the CTE mismatch that typically exists between a packaged die and a resin-impregnated fiberglass mounting substrate. In one embodiment, the system includes an underfill mixture that alone exhibits a CTE that is characteristic of an inorganic-filled underfill composite previously known. An embodiment is also directed to the assembly of a flip-chip package that uses an underfill mixture.

摘要翻译： 用于芯片封装中底部填充的系统包括底部填充混合物，其改善通常存在于包装的模具和浸渍树脂的玻璃纤维安装基板之间的CTE失配。 在一个实施方案中，该系统包括一种底部填充混合物，其单独表现出以前已知的无机填充的底部填充复合物的特征的CTE。 实施例还涉及使用底部填充混合物的倒装芯片封装的组装。

公开(公告)号：US20060105497A1

公开(公告)日：2006-05-18

申请号：US10990228

申请日：2004-11-15

申请人： Daewoong Suh ,  Saikumar Jayaraman

发明人： Daewoong Suh ,  Saikumar Jayaraman

IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L23/49816 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/15311 ,  H05K3/305 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/10977 ,  H05K2203/043 ,  H05K2203/0568 ,  Y02P70/613 ,  H01L2924/00

摘要： Methods of forming a microelectronic structure are described. Those methods comprise forming a stress compensation layer on a substrate, forming at least one opening within the stress compensation layer, and forming an interconnect paste within the at least one opening.

摘要翻译： 描述形成微电子结构的方法。 这些方法包括在衬底上形成应力补偿层，在应力补偿层内形成至少一个开口，以及在至少一个开口内形成互连膏。

公开(公告)号：US20060073344A1

公开(公告)日：2006-04-06

申请号：US10954651

申请日：2004-09-29

申请人： Saikumar Jayaraman

发明人： Saikumar Jayaraman

IPC分类号： B32B27/38 ,  C08L63/00 ,  H01L21/50 ,  H01L21/48

CPC分类号： H01L21/563 ,  B23K35/3613 ,  C08G59/44 ,  C08G59/687 ,  H01L23/296 ,  H01L24/29 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/83192 ,  H01L2224/83856 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H05K3/305 ,  H05K3/3489 ,  H05K2201/10734 ,  H05K2201/10977 ,  Y02P70/613 ,  Y10T428/31515 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： An underfill composition includes a thermosetting resin and a thermally cleavable component that releases sulfonic acid upon thermal activation. The underfill composition is applied to flip-chip technology during no-flow underfill mounting of the flip-chip to a mounting substrate. The mounting substrate can be further mounted on a board. A process includes formation of the underfill composition. A method includes assembly of the underfill composition with the flip-chip, and further can include assembly of the mounting substrate to a board. A computing system is also included that uses the underfill composition.

摘要翻译： 底部填充组合物包括热固性树脂和热裂解组分，其在热活化时释放磺酸。 在将倒装芯片的底部填充安装到安装基板的过程中，将底部填充组合物应用于倒装芯片技术。 安装基板可以进一步安装在板上。 一种方法包括形成底层填料组合物。 一种方法包括使用倒装芯片组装底部填充组合物，并且还可以包括将安装基板组装到板上。 还包括使用底部填充组合的计算系统。

公开(公告)号：US20060043614A1

公开(公告)日：2006-03-02

申请号：US11259994

申请日：2005-10-24

申请人： Saikumar Jayaraman

发明人： Saikumar Jayaraman

IPC分类号： H01L23/29 ,  H01L21/48

CPC分类号： C08G69/42 ,  C08G59/504 ,  H01L21/563 ,  H01L23/293 ,  H01L23/296 ,  H01L23/3128 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/0401

摘要： An apparatus including a first substrate comprising a first set of contact points; a second substrate including a second set of contact points coupled to the first substrate through interconnections between a portion of the first set of contact points a portion of the second set of contact points; and a composition disposed between the first substrate and the second substrate including a siloxane-based aromatic diamine.

公开(公告)号：US20050224951A1

公开(公告)日：2005-10-13

申请号：US10815565

申请日：2004-03-31

申请人： Daewoong Suh ,  Christos Economopoulos ,  Saikumar Jayaraman ,  Mohd Basiron ,  Sheau Lim ,  Yoong Chin

发明人： Daewoong Suh ,  Christos Economopoulos ,  Saikumar Jayaraman ,  Mohd Basiron ,  Sheau Lim ,  Yoong Chin

IPC分类号： H01L21/48 ,  H01L23/12 ,  H01L23/498 ,  H05K3/34

CPC分类号： H01L23/49816 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K3/3436 ,  H05K2201/0209 ,  H05K2201/10977 ,  H05K2203/0126 ,  Y02P70/613 ,  H01L2224/05599

摘要： A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a solder bump that is disposed upon the lower surface. The stress-relief layer flows against the solder bump. An article that exhibits a stress-relief layer with a structure characteristic of the manner of dispensing is also included. A computing system that includes a stress-relief layer with a structure characteristic of the manner of dispensing is also included.

摘要翻译： 通过在基底下表面上分配聚合物以部分地嵌入设置在下表面上的焊料凸块的条件来形成应力消除层。 应力消除层流向焊料凸块。 还包括具有分配方式结构特征的应力消除层的制品。 还包括包括具有分配方式的结构特征的应力消除层的计算系统。

公开(公告)号：US20050221534A1

公开(公告)日：2005-10-06

申请号：US10815968

申请日：2004-03-31

申请人： Daewoong Suh ,  Saikumar Jayaraman ,  Mohd Bin Basiron ,  Sheau Lim ,  Yoong P. Chin

发明人： Daewoong Suh ,  Saikumar Jayaraman ,  Mohd Bin Basiron ,  Sheau Lim ,  Yoong P. Chin

IPC分类号： H01L21/44 ,  H01L23/498 ,  H05K1/02 ,  H05K3/34

CPC分类号： H05K3/3436 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01077 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K2201/10977 ,  H05K2203/0126 ,  H05K2203/1189 ,  Y02P70/613 ,  H01L2224/05599

摘要： A stress-relief layer is formed by dispensing a polymer upon a substrate lower surface under conditions to partially embed a solder bump that is disposed upon the lower surface. The stress-relief layer flows against the solder bump. A stress-compensation collar is formed on a board to which the substrate is mated and the SCC partially embeds the solder bump. An article that exhibits a stress-relief layer and a stress-compensation collar is also included. A computing system that includes a stress-relief layer and a stress-compensation collar is also included.

摘要翻译： 通过在基底下表面上分配聚合物以部分地嵌入设置在下表面上的焊料凸块的条件来形成应力消除层。 应力消除层流向焊料凸块。 应力补偿轴环形成在与基板配合的板上，并且SCC部分地嵌入焊料凸块。 还包括展示应力消除层和应力补偿套环的物品。 还包括一个包括应力消除层和应力补偿环的计算系统。

公开(公告)号：US06926955B2

公开(公告)日：2005-08-09

申请号：US10071743

申请日：2002-02-08

申请人： Saikumar Jayaraman ,  Paul A. Koning ,  Ashay Dani

发明人： Saikumar Jayaraman ,  Paul A. Koning ,  Ashay Dani

IPC分类号： C08K3/08 ,  C08K3/22 ,  B23B5/16

CPC分类号： H01L23/3737 ,  C08K3/08 ,  C08K3/22 ,  H01L23/4275 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/16152 ,  Y10T29/49002 ,  Y10T29/49083 ,  Y10T29/49099 ,  Y10T29/4913 ,  Y10T428/12701 ,  Y10T428/12896 ,  Y10T428/23 ,  Y10T428/25 ,  Y10T428/252 ,  Y10T428/2982 ,  H01L2924/00

摘要： According to one aspect of the invention, a structure and method for providing improved thermal conductivity of a thermal interface material (TIM) made of phase changed polymer matrix and a fusible filler material is disclosed. The TIM may also have a non-fusible filler material and a percentage of a non-phase change polymer added to the phase change polymer matrix. The TIM, used to mate and conduct heat between two or more components, can be highly filled systems in a polymeric matrix where the fillers are thermally more conductive than the polymer matrix.

摘要翻译： 根据本发明的一个方面，公开了一种用于提供由相变聚合物基体和易熔填料制成的热界面材料（TIM）的改进导热性的结构和方法。 TIM还可以具有不可熔填料和添加到相变聚合物基质中的百分比的非相变聚合物。 用于在两个或多个组分之间配合和传导热量的TIM可以是聚合物基质中的高度填充体系，其中填料的热导率高于聚合物基质。

公开(公告)号：US20050068757A1

公开(公告)日：2005-03-31

申请号：US10676548

申请日：2003-09-30

申请人： Saikumar Jayaraman ,  Terry Sterrett ,  Connie Gettinger ,  Vijay Wakharkar ,  Agnes Padovani

发明人： Saikumar Jayaraman ,  Terry Sterrett ,  Connie Gettinger ,  Vijay Wakharkar ,  Agnes Padovani

IPC分类号： H01L23/498 ,  H05K1/02 ,  H05K3/34 ,  H05K1/11 ,  H05K1/14

CPC分类号： H01L23/49816 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K3/3436 ,  H05K2201/10977 ,  Y02P70/613

摘要： According to one aspect of the present invention, an electronic assembly and a method of forming an electronic assembly are provided. A semiconductor package includes a package substrate with a microelectronic die mounted to a first side and contact formations attached to a second side thereof. A stress compensation layer is formed on the first surface between the contact formations. The semiconductor package is then attached to a circuit board leaving an air space between the stress compensation layer and the circuit board. The stress compensation layer reduces stress on the contact formations and increases solder joint reliability.

摘要翻译： 根据本发明的一个方面，提供一种电子组件和一种形成电子组件的方法。 半导体封装包括具有安装到第一侧的微电子管芯的封装衬底和附接到其第二侧的接触结构。 在接触层之间的第一表面上形成应力补偿层。 然后，半导体封装被附接到电路板，留下应力补偿层和电路板之间的空气空间。 应力补偿层减少了接触层的应力，增加了焊点的可靠性。