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    Suppression of inclined defect formation and increase in critical thickness by silicon doping on non-c-plane (Al,Ga,In)N
    86.
    发明授权
    Suppression of inclined defect formation and increase in critical thickness by silicon doping on non-c-plane (Al,Ga,In)N 有权
    通过硅掺杂在非c面（Al，Ga，In）N上抑制倾斜缺陷形成和临界厚度增加

    公开(公告)号：US08772758B2

    公开(公告)日：2014-07-08

    申请号：US13470598

    申请日：2012-05-14

    申请人： Matthew T. Hardy ,  Po Shan Hsu ,  Steven P. DenBaars ,  James S. Speck ,  Shuji Nakamura

    发明人： Matthew T. Hardy ,  Po Shan Hsu ,  Steven P. DenBaars ,  James S. Speck ,  Shuji Nakamura

    IPC分类号： H01L29/06

    CPC分类号： H01L21/0254 ,  H01L21/02389 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/02513

    摘要： A method for fabricating a III-nitride based semiconductor device, including (a) growing one or more buffer layers on or above a semi-polar or non-polar GaN substrate, wherein the buffer layers are semi-polar or non-polar III-nitride buffer layers; and (b) doping the buffer layers so that a number of crystal defects in III-nitride device layers formed on or above the doped buffer layers is not higher than a number of crystal defects in III-nitride device layers formed on or above one or more undoped buffer layers. The doping can reduce or prevent formation of misfit dislocation lines and additional threading dislocations. The thickness and/or composition of the buffer layers can be such that the buffer layers have a thickness near or greater than their critical thickness for relaxation. In addition, one or more (AlInGaN) or III-nitride device layers can be formed on or above the buffer layers.

    摘要翻译： 一种用于制造III族氮化物的半导体器件的方法，包括（a）在半极性或非极性GaN衬底上或之上生长一个或多个缓冲层，其中缓冲层是半极性或非极性III- 氮化物缓冲层; 并且（b）掺杂缓冲层，使得形成在掺杂缓冲层上或上方的III族氮化物器件层中的多个晶体缺陷不高于形成在一个或多个第一或第二晶体管上形成的III族氮化物器件层中的多个晶体缺陷 更多未掺杂的缓冲层。 掺杂可以减少或防止错配位错线的形成和额外的穿线位错。 缓冲层的厚度和/或组成可以使得缓冲层的厚度接近或大于其缓解的临界厚度。 此外，可以在缓冲层上或上方形成一个或多个（AlInGaN）或III族氮化物器件层。

    LED with current confinement structure and surface roughening
    90.
    发明授权
    LED with current confinement structure and surface roughening 有权
    LED具有电流限制结构和表面粗糙化

    公开(公告)号：US08541788B2

    公开(公告)日：2013-09-24

    申请号：US12581759

    申请日：2009-10-19

    申请人： Steven P. Denbaars ,  Shuji Nakamura ,  Max Batres

    发明人： Steven P. Denbaars ,  Shuji Nakamura ,  Max Batres

    IPC分类号： H01L27/15

    CPC分类号： H01L33/42 ,  H01L33/145 ,  H01L33/22 ,  H01L33/405

    摘要： A light emitting diode having a vertical orientation with an ohmic contact on portions of a top surface of the diode and a reflective layer adjacent the light emitting region of the diode. This light emitting diode includes a confinement structure. The confinement structure may be an opening in the reflective layer generally beneath the top ohmic contact that defines a non-contact area between the reflective layer and the light emitting region of the diode to encourage current flow to take place other than at the non-contact area to in turn decrease the number of light emitting recombinations beneath the ohmic contact and increase the number of light emitting recombinations in the areas not beneath said ohmic contact. The LED may include roughened emitting surfaces to further enhance light extraction.

    摘要翻译： 具有在二极管的顶表面的部分上的欧姆接触的垂直取向的发光二极管和与二极管的发光区相邻的反射层。 该发光二极管包括限制结构。 约束结构可以是反射层中通常在顶部欧姆接触下方的开口，其限定反射层和二极管的发光区域之间的非接触区域，以促进除非接触之外的电流流动 面积又减少欧姆接触下方的发光复合数，并增加不在所述欧姆接触下方的区域中的发光复合数。 LED可以包括粗糙化的发射表面以进一步增强光提取。