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117 条记录 (耗时 0.033 秒)

    Accelerated plasma clean
    82.
    发明申请
    Accelerated plasma clean 有权
    加速等离子清洁

    公开(公告)号：US20050103266A1

    公开(公告)日：2005-05-19

    申请号：US10968420

    申请日：2004-10-18

    申请人： Shankar Chandran ,  Scott Hendrickson ,  Gwendolyn Jones ,  Shankar Venkataraman ,  Ellie Yieh

    发明人： Shankar Chandran ,  Scott Hendrickson ,  Gwendolyn Jones ,  Shankar Venkataraman ,  Ellie Yieh

    IPC分类号： B08B9/08 ,  C23C16/44 ,  H01L21/304 ,  C25F1/00 ,  C23C16/00

    CPC分类号： C23C16/4405 ,  Y10S134/902 ,  Y10S438/905

    摘要： A method and apparatus that reduces the time required to clean a processing chamber employing a reactive plasma cleaning process. A plasma is formed in an Astron fluorine source generator from a flow of substantially pure inert-source gas. After formation of the plasma, a flow of a fluorine source gas is introduced therein such that the fluorine source flow accelerates at a rate no greater than 1.67 standard cubic centimeters per second2 (scc/s2). In this fashion, the plasma contains a plurality of radicals and dissociated inert-source gas atoms, defining a cleaning mixture. The ratio of inert-source gas to fluorine source is greater than 1:1.

    摘要翻译： 一种减少使用反应性等离子体清洗工艺清洁处理室所需时间的方法和装置。 在基本上纯的惰性气体气体的流中，在Astron氟源发生器中形成等离子体。 在形成等离子体之后，引入氟源气体的流动，使得氟源流以不大于1.67标准立方厘米/秒的速度加速（scc / s < 2 ）。 以这种方式，等离子体包含多个自由基和解离的惰性气体原子，限定清洁混合物。 惰性气体与氟源的比例大于1:1。

    Double patterning etching process
    87.
    发明授权
    Double patterning etching process 有权
    双图案蚀刻工艺

    公开(公告)号：US08759223B2

    公开(公告)日：2014-06-24

    申请号：US13593412

    申请日：2012-08-23

    申请人： Kedar Sapre ,  Jing Tang ,  Ajay Bhatnagar ,  Nitin Ingle ,  Shankar Venkataraman

    发明人： Kedar Sapre ,  Jing Tang ,  Ajay Bhatnagar ,  Nitin Ingle ,  Shankar Venkataraman

    IPC分类号： H01L21/311 ,  H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/31144 ,  H01J37/32357 ,  H01J2237/334 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31116

    摘要： A method of etching a substrate comprises forming on the substrate, a plurality of double patterning features composed of silicon oxide, silicon nitride, or silicon oxynitride. The substrate having the double patterning features is provided to a process zone. An etching gas comprising nitrogen tri-fluoride, ammonia and hydrogen is energized in a remote chamber. The energized etching gas is introduced into the process zone to etch the double patterning features to form a solid residue on the substrate. The solid residue is sublimated by heating the substrate to a temperature of at least about 100° C.

    摘要翻译： 蚀刻衬底的方法包括在衬底上形成由氧化硅，氮化硅或氮氧化硅组成的多个双重构图特征。 具有双重图案化特征的基板被提供到处理区域。 包括三氟化氮，氨和氢的蚀刻气体在远程室中通电。 通电的蚀刻气体被引入到工艺区中以蚀刻双重图案化特征以在衬底上形成固体残余物。 固体残余物通过将基底加热至至少约100℃的温度升华。

    Two silicon-containing precursors for gapfill enhancing dielectric liner
    89.
    发明授权
    Two silicon-containing precursors for gapfill enhancing dielectric liner 有权
    两种含硅前体，用于填隙增强电介质衬垫

    公开(公告)号：US08664127B2

    公开(公告)日：2014-03-04

    申请号：US13182671

    申请日：2011-07-14

    申请人： Sidharth Bhatia ,  Hiroshi Hamana ,  Paul Edward Gee ,  Shankar Venkataraman

    发明人： Sidharth Bhatia ,  Hiroshi Hamana ,  Paul Edward Gee ,  Shankar Venkataraman

    IPC分类号： H01L21/00

    CPC分类号： H01L21/76224 ,  B82Y10/00 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02222 ,  H01L21/02271

    摘要： Aspects of the disclosure pertain to methods of depositing silicon oxide layers on substrates. In embodiments, silicon oxide layers are deposited by flowing a silicon-containing precursor having a Si—O bond, an oxygen-containing precursor and a second silicon-containing precursor, having both a Si—C bond and a Si—N bond, into a semiconductor processing chamber to form a conformal liner layer. Upon completion of the liner layer, a gap fill layer is formed by flowing a silicon-containing precursor having a Si—O bond, an oxygen-containing precursor into the semiconductor processing chamber. The presence of the conformal liner layer improves the ability of the gap fill layer to grow more smoothly, fill trenches and produce a reduced quantity and/or size of voids within the silicon oxide filler material.

    摘要翻译： 本公开的方面涉及在衬底上沉积氧化硅层的方法。 在实施例中，通过将具有Si-O键的含硅前体，含氧前体和具有Si-C键和Si-N键的第二含硅前体流过，沉积氧化硅层， 半导体处理室以形成保形衬里层。 在衬里层完成时，通过将具有Si-O键的含硅前体，含氧前体流入半导体处理室来形成间隙填充层。 保形衬垫层的存在提高了间隙填充层更平稳地生长，填充沟槽并且在氧化硅填料材料内产生减少量和/或尺寸的空隙的能力。

    Post-planarization densification
    90.
    发明授权
    Post-planarization densification 有权
    后平面化致密化

    公开(公告)号：US08466067B2

    公开(公告)日：2013-06-18

    申请号：US13043131

    申请日：2011-03-08

    申请人： Jingmei Liang ,  Nitin K. Ingle ,  Shankar Venkataraman

    发明人： Jingmei Liang ,  Nitin K. Ingle ,  Shankar Venkataraman

    IPC分类号： H01L21/311

    CPC分类号： H01L21/02164 ,  H01L21/02337 ,  H01L21/3105 ,  H01L21/31055 ,  H01L21/316 ,  H01L21/76229

    摘要： Processes for forming high density gap-filling silicon oxide on a patterned substrate are described. The processes increase the density of gap-filling silicon oxide particularly in narrow trenches. The density may also be increased in wide trenches and recessed open areas. The densities of the gap-filling silicon oxide in the narrow and wide trenches/open areas become more similar following the treatment which allows the etch rates to match more closely. This effect may also be described as a reduction in the pattern loading effect. The process involves forming then planarizing silicon oxide. Planarization exposes a new dielectric interface disposed closer to the narrow trenches. The newly exposed interface facilitates a densification treatment by annealing and/or exposing the planarized surface to a plasma.

    摘要翻译： 描述了在图案化衬底上形成高密度间隙填充氧化硅的工艺。 这些工艺增加了间隙填充氧化硅的密度，特别是在狭窄的沟槽中。 在宽的沟槽和凹入的开放区域中，密度也可以增加。 狭缝和宽沟槽/开放区域中填充间隙的氧化硅的密度在处理之后变得更加相似，这允许蚀刻速率更紧密地匹配。 这种效果也可以被描述为模式加载效应的降低。 该方法涉及形成二氧化硅平坦化。 平面化暴露出更靠近窄沟槽设置的新介质界面。 新暴露的界面通过将平坦化表面退火和/或暴露于等离子体来促进致密化处理。