公开(公告)号：US11855003B2

公开(公告)日：2023-12-26

申请号：US17320179

申请日：2021-05-13

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Pu Wang ,  Li-Hui Cheng ,  Szu-Wei Lu ,  Hsien-Ju Tsou

IPC分类号： H01L21/48 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L21/683 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31

CPC分类号： H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0655 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/19103 ,  H01L2924/3511

摘要： A method of fabricating an integrated fan-out package is provided. A ring-shaped dummy die and a group of integrated circuit dies are mounted over a carrier, wherein the group of integrated circuit dies are surrounded by the ring-shaped dummy die. The ring-shaped dummy die and the group of integrated circuit dies over the carrier are encapsulated with an insulating encapsulation. A redistribution circuit structure is formed on the ring-shaped dummy die, the group of integrated circuit dies and the insulating encapsulation, wherein the redistribution circuit structure is electrically connected to the group of integrated circuit dies, and the ring-shaped dummy die is electrically floating.

公开(公告)号：US11854992B2

公开(公告)日：2023-12-26

申请号：US17530868

申请日：2021-11-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Chen-Hua Yu ,  Kai-Chiang Wu ,  Chun-Lin Lu

IPC分类号： H01L23/538 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L25/00

CPC分类号： H01L23/5389 ,  H01L21/565 ,  H01L21/566 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L25/0652 ,  H01L25/50 ,  H01L21/568 ,  H01L2224/04105 ,  H01L2224/08225 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/73267 ,  H01L2224/80006 ,  H01L2924/15192

摘要： A method of manufacturing a semiconductor structure includes following operations. A first die is provided. A first molding is formed to encapsulate the first die. A second die is disposed over the first molding. A mold chase is disposed over the second die and the first molding. The mold chase includes a protrusion protruded from the mold chase towards the first molding. A molding material is disposed between the mold chase and the first molding. A second molding is formed to surround the second die. The second die is at least partially covered by the second molding. The disposing of the mold chase includes surrounding the protrusion of the mold chase by the molding material.

公开(公告)号：US11854989B2

公开(公告)日：2023-12-26

申请号：US17167789

申请日：2021-02-04

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Dongho Kim ,  Jongbo Shim ,  Hwan Pil Park ,  Choongbin Yim ,  Jungwoo Kim

IPC分类号： H01L23/538 ,  H01L23/13 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L25/065

CPC分类号： H01L23/5389 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/20 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/214 ,  H01L2225/0651 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/19103

摘要： A semiconductor package substrate includes a substrate having a bottom surface including a cavity structure defined therein. The cavity structure includes a floor surface. A passive device structure has at least a partial portion of the passive device structure disposed in the cavity structure. The passive device structure includes a first passive device and a second passive device that are each electrically connected to the floor surface of the cavity structure. At least partial portions of the first passive device and the second passive device vertically overlap each other.

公开(公告)号：US11854927B2

公开(公告)日：2023-12-26

申请号：US17333399

申请日：2021-05-28

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Ting-Chen Tseng ,  Sih-Hao Liao ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L21/311 ,  H01L21/56

CPC分类号： H01L23/3185 ,  H01L21/31133 ,  H01L21/56 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/221

摘要： A package and a method forming the same are provided. The package includes an integrated circuit die. A sidewall of the integrated circuit die has a first facet and a second facet. The first facet and the second facet have different slopes. The package includes an encapsulant surrounding the integrated circuit die and in physical contact with the first facet and the second facet and an insulating layer over the integrated circuit die and the encapsulant. An upper surface of the integrated circuit die is lower than an upper surface of the encapsulant. A sidewall of the insulating layer is substantially coplanar with the first facet.

公开(公告)号：US11854877B2

公开(公告)日：2023-12-26

申请号：US17215493

申请日：2021-03-29

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Jing-Cheng Lin ,  Ying-Ching Shih ,  Pu Wang ,  Chen-Hua Yu

IPC分类号： H01L21/768 ,  H01L21/56 ,  H01L21/683 ,  H01L25/065 ,  H01L23/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/48 ,  H01L25/00

CPC分类号： H01L21/76877 ,  H01L21/561 ,  H01L21/563 ,  H01L21/565 ,  H01L21/6835 ,  H01L21/76802 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/3157 ,  H01L23/481 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L21/568 ,  H01L23/3128 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/92 ,  H01L2221/68359 ,  H01L2224/16113 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48229 ,  H01L2224/73267 ,  H01L2224/8385 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/2919 ,  H01L2924/0655 ,  H01L2924/13091 ,  H01L2924/00

摘要： Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes: a bottom package; wherein an area of a contact surface between the conductor and the through via substantially equals a cross-sectional area of the through via, and the bottom package includes: a molding compound; a through via penetrating through the molding compound; a die molded in the molding compound; and a conductor on the through via. An associated method of manufacturing the semiconductor device is also disclosed.

公开(公告)号：US20230411334A1

公开(公告)日：2023-12-21

申请号：US17865586

申请日：2022-07-15

申请人： BOARDTEK ELECTRONICS CORPORATION

发明人： CHIEN-CHENG LEE

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L23/367 ,  H01L21/48

CPC分类号： H01L24/20 ,  H01L24/32 ,  H01L24/19 ,  H01L23/49827 ,  H01L23/367 ,  H01L21/486 ,  H01L21/4867 ,  H01L24/29 ,  H01L2224/29339 ,  H01L24/83 ,  H01L2224/83192 ,  H01L2224/83201 ,  H01L2224/19 ,  H01L2224/211

摘要： A high-frequency power module less vulnerable to parasitic phenomena includes first base board, power chip, and second base board. The first base board includes a first substrate, a first conductive wiring layer, and a second conductive wiring layer on each side of the first substrate. The power chip is disposed on the first conductive wiring layer. The second base board includes a second substrate covering the power chip and the first conductive wiring layer, and a third conductive wiring layer away from the first conductive wiring layer. First conductive structures penetrate the second substrate to connect the third conductive wiring layer with the power chip, greatly reducing the lengths of signal paths between components and so parasitic effects A second conductive structure penetrates the first and second substrates to connect the first, second, and third conductive wiring layers. A manufacturing method is also disclosed.

公开(公告)号：US20230411247A1

公开(公告)日：2023-12-21

申请号：US18460632

申请日：2023-09-04

申请人： AT&S Austria Technologie & Systemtechnik Aktiengesellschaft

发明人： Roland Wilfing

IPC分类号： H01L23/48 ,  H01L23/00

CPC分类号： H01L23/481 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2224/19

摘要： A component carrier includes a stack having at least one electrically conductive layer structure and at least one electrically insulating layer structure. At least one of the at least one electrically insulating layer structure(s) has at least partly tapered through holes filled substantially completely with an electrically conductive filling. The at least one electrically conductive layer structure and the electrically conductive filling are made of the same material. Different ones of the through holes of one electrically insulating layer structure are tapering in opposite directions.

公开(公告)号：US20230395452A1

公开(公告)日：2023-12-07

申请号：US17811909

申请日：2022-07-12

申请人： InnoLux Corporation

发明人： Cheng-Chi WANG ,  Chin-Ming HUANG ,  Yi-Reng CHEN

IPC分类号： H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC分类号： H01L23/3192 ,  H01L24/20 ,  H01L24/19 ,  H01L24/96 ,  H01L21/561 ,  H01L21/566 ,  H01L2924/3512 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/95001 ,  H01L2924/3511 ,  H01L23/3171

摘要： An electronic device and a manufacturing method thereof are provided. The electronic device includes an electronic unit, a first insulating layer, a second insulating layer and a connecting element. The electronic unit includes a first surface, a second surface opposite to the first surface, and a first side surface connecting the first surface to the second surface. The first insulating layer is disposed on the second surface. The second insulating layer is disposed on the first insulating layer. The second insulating layer includes a third surface, a fourth surface opposite to the third surface, and a second side surface connecting the third surface to the fourth surface. The connecting element is disposed on the second insulating layer and is electrically connected to the electronic unit. The third surface of the second insulating layer is in contact with the second surface of the electronic unit.

公开(公告)号：US11837587B2

公开(公告)日：2023-12-05

申请号：US17567169

申请日：2022-01-03

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Wei-Yu Chen ,  An-Jhih Su ,  Chi-Hsi Wu ,  Der-Chyang Yeh ,  Li-Hsien Huang ,  Po-Hao Tsai ,  Ming-Shih Yeh ,  Ta-Wei Liu

IPC分类号： H01L25/10 ,  H01L23/48 ,  H01L23/00 ,  H01L23/31 ,  H01L21/768 ,  H01L25/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/538 ,  H01L25/065

CPC分类号： H01L25/105 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/76802 ,  H01L23/3121 ,  H01L23/3142 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/19 ,  H01L24/20 ,  H01L24/24 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L23/3128 ,  H01L24/48 ,  H01L25/0657 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/211 ,  H01L2224/24145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/1436 ,  H01L2924/00012 ,  H01L2924/1433 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2224/45099 ,  H01L2924/181 ,  H01L2924/00012

摘要： A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

公开(公告)号：US11837550B2

公开(公告)日：2023-12-05

申请号：US17215079

申请日：2021-03-29

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chen-Hua Yu ,  Chung-Shi Liu ,  Chih-Wei Lin ,  Ming-Da Cheng

IPC分类号： H01L23/538 ,  H01L21/56 ,  H01L23/498 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00 ,  H01L21/60

CPC分类号： H01L23/5384 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/49805 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L24/73 ,  H01L24/92 ,  H01L25/105 ,  H01L21/568 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/32 ,  H01L24/83 ,  H01L2021/6006 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/27334 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1533 ,  H01L2924/15311 ,  H01L2224/19 ,  H01L2224/83005

摘要： A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.