公开(公告)号：US06905961B2

公开(公告)日：2005-06-14

申请号：US10336579

申请日：2003-01-03

申请人： David Vincent Caletka ,  Krishna Darbha ,  William Infantolino ,  Eric Arthur Johnson

发明人： David Vincent Caletka ,  Krishna Darbha ,  William Infantolino ,  Eric Arthur Johnson

IPC分类号： H01L23/498 ,  H01L21/44

CPC分类号： H01L23/4985 ,  H01L2224/16 ,  H01L2924/01087 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/00

摘要： A flexible chip carrier with contact pads on its upper surface matching those of the chip with said pads conductively connected to land grid array (LGA) pads on its lower surface matching the those of a card or PCB. The chip carrier is provided with a stiffening layer at the LGA interface. The stiffening layer is mechanically attached to the lower surface of the chip carrier. Holes are formed in the stiffening layer to expose the LGA pads. The holes are then filled with a conductive adhesive material. Compliant LGA bumps are applied to the uncured conductive adhesive material which material is then cured.

摘要翻译： 具有在其上表面上具有接触焊盘的柔性芯片载体，其与所述芯片的接触焊盘匹配，所述焊盘导电地连接到其下表面上与卡或PCB匹配的焊盘格栅阵列（LGA）焊盘。 芯片载体在LGA接口处设有加强层。 加强层机械地附接到芯片载体的下表面。 在加强层中形成孔以暴露LGA垫。 然后用导电粘合剂材料填充孔。 对未固化的导电粘合剂材料施加合适的LGA凸块，该材料然后被固化。

公开(公告)号：US20080119029A1

公开(公告)日：2008-05-22

申请号：US12015604

申请日：2008-01-17

申请人： David Vincent Caletka ,  Seungbae Park ,  Sanjeev Balwant Sathe

发明人： David Vincent Caletka ,  Seungbae Park ,  Sanjeev Balwant Sathe

IPC分类号： H01L21/304

CPC分类号： H01L24/29 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/02319 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/10122 ,  H01L2224/11001 ,  H01L2224/16111 ,  H01L2224/16225 ,  H01L2224/29 ,  H01L2224/29011 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/81138 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83194 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/30107 ,  H05K3/3436 ,  H05K2201/10977 ,  H05K2201/2036 ,  Y02P70/613 ,  Y10S438/94 ,  Y10S438/977 ,  H01L2924/00 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/01082 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2924/00012 ,  H01L2224/81805

摘要： A chip module having a chip with a flexible multilayer redistribution thin film attached thereto for connection to a substrate. The thin film acts as both a redistribution medium with multiple layers of redistribution metallurgy for chip power and signals and as a compliant medium to relieve stresses caused by thermal expansion mismatch between chip and substrate. Modules comprising chip and thin film may be fabricated at the chip or wafer level. The upper surface of the thin film has an array of pads matching the array of pads on the chip or wafer while the lower surface has pads matching those of the substrate. The multilayer thin film is first formed on a temporary substrate and then the chip is to the thin film before release from the temporary substrate. After release, the module is ready for mounting to the second level packaging substrate, such as a chip carrier or PCB. Where the multilayer thin film is formed directly on a wafer, the wafer is then diced to form the module.

摘要翻译： 一种芯片模块，具有连接到基板上的具有柔性多层再分布薄膜的芯片。 该薄膜同时具有用于芯片功率和信号的具有多层再分配冶金的再分配介质，并且作为缓解由芯片和衬底之间的热膨胀失配引起的应力的柔性介质。 包括芯片和薄膜的模块可以在芯片或晶片级制造。 薄膜的上表面具有与芯片或晶片上的焊盘阵列匹配的焊盘阵列，而下表面具有与衬底相匹配的焊盘。 首先在临时衬底上形成多层薄膜，然后在从临时衬底释放之前将芯片放在薄膜上。 释放后，模块已准备好安装到第二级封装基板，如芯片载体或PCB。 在多层薄膜直接形成在晶片上的情况下，切割晶片以形成模块。

公开(公告)号：US6051982A

公开(公告)日：2000-04-18

申请号：US826962

申请日：1997-04-09

申请人： David James Alcoe ,  David Vincent Caletka

发明人： David James Alcoe ,  David Vincent Caletka

IPC分类号： G01R1/067 ,  G01R1/073 ,  G01R31/02

CPC分类号： G01R1/07314 ,  G01R1/06733 ,  G01R1/07392

摘要： A test apparatus including at least one probe member precisely aligned using two spaced apart means (e.g., thin layers) such that the probe can effectively engage a conductor (e.g., solder ball) on an electronic module (e.g., ball grid array package). A compressible member (e.g., elastomeric body) is used to bias the probe toward the conductor. Various probe cross-sectional configurations are also provided. As taught herein, the probe electrically contacts one of the spaced apart means, also conductive, to thus form a circuit which can extend externally of the apparatus (e.g., for connecting to appropriate testing equipment).

摘要翻译： 一种测试装置，其包括使用两个间隔开的装置（例如薄层）精确对准的至少一个探针构件，使得探针可以有效地接合电子模块（例如，球栅阵列封装）上的导体（例如，焊球）。 使用可压缩构件（例如，弹性体）将探针偏压到导体。 还提供了各种探针横截面构造。 如本文所教导的，探针电接触一个间隔开的装置，也是导电的，从而形成可延伸到设备外部（例如，用于连接到适当的测试设备）的电路。

公开(公告)号：US5947750A

公开(公告)日：1999-09-07

申请号：US848949

申请日：1997-04-30

申请人： David James Alcoe ,  William Louis Brodsky ,  David Vincent Caletka

发明人： David James Alcoe ,  William Louis Brodsky ,  David Vincent Caletka

IPC分类号： H01R12/62 ,  H05K3/36 ,  H01R9/09

CPC分类号： H01R12/62 ,  H05K3/365

摘要： An elastomeric structure including two layers, the first having patterned openings therein and adjacent web members, the second including a patterned array of upstanding projections. The openings and projections may be of cylindrical, rectangular, or other configurations and are oriented in highly dense patterns. The elastomeric is positioned with and attached to a base member having a sidewall substantially as high as the corresponding external side surface of the elastomeric's first layer. The sidewall constrains the elastomeric during compression. The invention thereby substantially prevents lateral expansion of the elastomeric's side surface and lateral deflection of both layers, resulting in a uniform distribution of compressive forces on the upstanding projections.

摘要翻译： 包括两层的弹性体结构，其中第一层具有图案化的开口和相邻的腹板构件，第二层包括直立突起的图案化阵列。 开口和突起可以是圆柱形，矩形或其它构造，并且以高致密图案取向。 弹性体被定位并且附接到具有基本上与弹性体的第一层的对应外侧表面一样高的侧壁的基底构件。 侧壁在压缩过程中约束弹性体。 因此，本发明基本上防止了弹性体的侧面的横向膨胀和两层的横向偏转，从而导致对直立突起的压缩力的均匀分布。

公开(公告)号：US5804984A

公开(公告)日：1998-09-08

申请号：US691732

申请日：1996-08-02

申请人： David James Alcoe ,  David Vincent Caletka

发明人： David James Alcoe ,  David Vincent Caletka

IPC分类号： G01R1/067 ,  G01R1/073 ,  G01R31/02

CPC分类号： G01R1/06733 ,  G01R1/07314 ,  G01R1/07392

摘要： A test apparatus including at least one probe member precisely aligned using two spaced apart means (e.g., thin dielectric layers having copper thereon) such that the probe can effectively engage a conductor (e.g., solder ball) on an electronic module (e.g., ball grid array package). A compressible member (e.g., elastomeric body) is used to bias the probe toward the conductor. Various probe cross-sectional configurations are also provided.

摘要翻译： 一种测试装置，其包括使用两个间隔开的装置（例如，其上具有铜的薄介电层）精确对准的至少一个探针构件，使得探针可以有效地接合电子模块（例如，球栅）上的导体（例如，焊球） 阵列包）。 使用可压缩构件（例如，弹性体）将探针偏压到导体。 还提供了各种探针横截面构造。

公开(公告)号：US07348261B2

公开(公告)日：2008-03-25

申请号：US10438947

申请日：2003-05-15

申请人： David Vincent Caletka ,  Seungbae Park ,  Sanjeev Balwant Sathe

发明人： David Vincent Caletka ,  Seungbae Park ,  Sanjeev Balwant Sathe

IPC分类号： H01L21/30 ,  H01L21/46 ,  H01L21/469

CPC分类号： H01L24/29 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/02319 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/10122 ,  H01L2224/11001 ,  H01L2224/16111 ,  H01L2224/16225 ,  H01L2224/29 ,  H01L2224/29011 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/81138 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83194 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/30107 ,  H05K3/3436 ,  H05K2201/10977 ,  H05K2201/2036 ,  Y02P70/613 ,  Y10S438/94 ,  Y10S438/977 ,  H01L2924/00 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/01082 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2924/00012 ,  H01L2224/81805

摘要： A chip module having a chip with a flexible multilayer redistribution thin film attached thereto for connection to a substrate. The thin film acts as both a redistribution medium with multiple layers of redistribution metallurgy for chip power and signals and as a compliant medium to relieve stresses caused by thermal expansion mismatch between chip and substrate. Modules comprising chip and thin film may be fabricated at the chip or wafer level. The upper surface of the thin film has an array of pads matching the array of pads on the chip or wafer while the lower surface has pads matching those of the substrate. The multilayer thin film is first formed on a temporary substrate and then the chip is attached to the thin film before release from the temporary substrate. After release, the module is ready for mounting to the second level packaging substrate, such as a chip carrier or PCB. Where the multilayer thin film is formed directly on a wafer, the wafer is then diced to form the module.

摘要翻译： 一种芯片模块，具有连接到基板上的具有柔性多层再分布薄膜的芯片。 该薄膜同时具有用于芯片功率和信号的具有多层再分配冶金的再分配介质，并且作为缓解由芯片和衬底之间的热膨胀失配引起的应力的柔顺介质。 包括芯片和薄膜的模块可以在芯片或晶片级制造。 薄膜的上表面具有与芯片或晶片上的焊盘阵列匹配的焊盘阵列，而下表面具有与衬底相匹配的焊盘。 首先在临时衬底上形成多层薄膜，然后在从临时衬底释放之前将芯片附着到薄膜上。 释放后，模块已准备好安装到第二级封装基板，如芯片载体或PCB。 在多层薄膜直接形成在晶片上的情况下，切割晶片以形成模块。

公开(公告)号：US06595784B2

公开(公告)日：2003-07-22

申请号：US09855308

申请日：2001-05-15

申请人： William Louis Brodsky ,  David Vincent Caletka

发明人： William Louis Brodsky ,  David Vincent Caletka

IPC分类号： H01R1200

CPC分类号： H05K1/036 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K1/113 ,  H05K1/114 ,  H05K1/141 ,  H05K3/42 ,  H05K3/4644 ,  H05K2201/0133 ,  H05K2201/0154 ,  H05K2201/09063 ,  H05K2201/10378 ,  H01L2924/00

摘要： An interposer member having strategically positioned apertures for electrically connecting an electronic device to a circuitized substrate. The member includes a homogeneous elastomer core having strategically positioned apertures. The apertures are positioned through the member approximately equidistant between adjacent plated through holes and/or conductive pads. Such positioning relieves stress from the plated through holes and/or conductive pads, and increases the contact compliancy of the member.

公开(公告)号：US06528892B2

公开(公告)日：2003-03-04

申请号：US09874196

申请日：2001-06-05

申请人： David Vincent Caletka ,  Krishna NMN Darbha ,  William NMN Infantolino ,  Eric Arthur Johnson

发明人： David Vincent Caletka ,  Krishna NMN Darbha ,  William NMN Infantolino ,  Eric Arthur Johnson

IPC分类号： H01L2348

CPC分类号： H01L23/4985 ,  H01L2224/16 ,  H01L2924/01087 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/00

摘要： A flexible chip carrier with contact pads on its upper surface matching those of the chip with said pads conductively connected to land grid array (LGA) pads on its lower surface matching the those of a card or PCB. The chip carrier is provided with a stiffening layer at the LGA interface. The stiffening layer is mechanically attached to the lower surface of the chip carrier. Holes are formed in the stiffening layer to expose the LGA pads. The holes are then filled with a conductive adhesive material. Compliant LGA bumps are applied to the uncured conductive adhesive material which material is then cured.

公开(公告)号：US06686664B2

公开(公告)日：2004-02-03

申请号：US09845448

申请日：2001-04-30

申请人： David Vincent Caletka ,  Krishna Darbha ,  Donald W. Henderson ,  Lawrence P. Lehman ,  George Henry Thiel

发明人： David Vincent Caletka ,  Krishna Darbha ,  Donald W. Henderson ,  Lawrence P. Lehman ,  George Henry Thiel

IPC分类号： H01L2348

CPC分类号： H01L23/49811 ,  B23K3/0623 ,  B23K2101/40 ,  H01L21/563 ,  H01L23/13 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05026 ,  H01L2224/05078 ,  H01L2224/05551 ,  H01L2224/05568 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/8121 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/92125 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15787 ,  H05K1/113 ,  H05K3/284 ,  H05K3/3436 ,  H05K2201/0116 ,  H05K2201/0133 ,  H05K2201/0382 ,  H05K2201/068 ,  H05K2201/09036 ,  H05K2201/09509 ,  H05K2201/0969 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/613 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49149 ,  Y10T29/49171 ,  H01L2924/00011 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/05552

摘要： Solder balls, such as, low melt C4 solder balls undergo volume expansion during reflow. Where the solder balls are encapsulated, expansion pressure can cause damage to device integrity. A volume expansion region in the semiconductor chip substrate beneath each of the solder balls accommodates volume expansion. Air-cushioned diaphgrams, deformable materials and non-wettable surfaces may be used to permit return of the solder during cooling to its original site. A porous medium with voids sufficient to accommodate expansion may also be used.

摘要翻译： 诸如低熔点C4焊球的焊球在回流期间经历体积膨胀。 当焊球被封装时，膨胀压力可能会损坏器件的完整性。 每个焊球下方的半导体芯片基板中的体积扩展区容纳体积膨胀。 可以使用气垫缓冲图，可变形材料和不可润湿的表面，以允许在冷却期间焊料返回到其原始位置。 也可以使用具有足以适应膨胀的空隙的多孔介质。

公开(公告)号：US06627998B1

公开(公告)日：2003-09-30

申请号：US09626904

申请日：2000-07-27

申请人： David Vincent Caletka ,  Seungbae Park ,  Sanjeev Balwant Sathe

发明人： David Vincent Caletka ,  Seungbae Park ,  Sanjeev Balwant Sathe

IPC分类号： H01L2348

CPC分类号： H01L24/29 ,  H01L21/563 ,  H01L23/3114 ,  H01L23/525 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/02319 ,  H01L2224/02333 ,  H01L2224/0401 ,  H01L2224/10122 ,  H01L2224/11001 ,  H01L2224/16111 ,  H01L2224/16225 ,  H01L2224/29 ,  H01L2224/29011 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29299 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/81138 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83194 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01076 ,  H01L2924/01078 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/1579 ,  H01L2924/30107 ,  H05K3/3436 ,  H05K2201/10977 ,  H05K2201/2036 ,  Y02P70/613 ,  Y10S438/94 ,  Y10S438/977 ,  H01L2924/00 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01083 ,  H01L2924/01082 ,  H01L2224/13111 ,  H01L2924/00014 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2924/00012 ,  H01L2224/81805

摘要： A chip module having a chip with a flexible multilayer redistribution thin film attached thereto for connection to a substrate. The thin film acts as both a redistribution medium with multiple layers of redistribution metallurgy for chip power and signals and as a compliant medium to relieve stresses caused by thermal expansion mismatch between chip and substrate. Modules comprising chip and thin film may be fabricated at the chip or wafer level. The upper surface of the thin film has an array of pads matching the array of pads on the chip or wafer while the lower surface has pads matching those of the substrate. The multilayer thin film is first formed on a temporary substrate and then the chip is attached to the thin film before release from the temporary substrate. After release, the module is ready for mounting to the second level packaging substrate, such as a chip carrier or PCB. Where the multilayer thin film is formed directly on a wafer, the wafer is then diced to form the module.

摘要翻译： 一种芯片模块，具有连接到基板上的具有柔性多层再分布薄膜的芯片。 该薄膜同时具有用于芯片功率和信号的具有多层再分配冶金的再分配介质，并且作为缓解由芯片和衬底之间的热膨胀失配引起的应力的柔顺介质。 包括芯片和薄膜的模块可以在芯片或晶片级制造。 薄膜的上表面具有与芯片或晶片上的焊盘阵列匹配的焊盘阵列，而下表面具有与衬底相匹配的焊盘。 首先在临时衬底上形成多层薄膜，然后在从临时衬底释放之前将芯片附着到薄膜上。 释放后，模块已准备好安装到第二级封装基板，如芯片载体或PCB。 在多层薄膜直接形成在晶片上的情况下，切割晶片以形成模块。