公开(公告)号：US09287137B2

公开(公告)日：2016-03-15

申请号：US13630901

申请日：2012-09-28

Applicant: Qunhua Wang ,  Weijie Wang ,  Young Jin Choi ,  Seon-Mee Cho ,  Yi Cui ,  Beom Soo Park ,  Soo Young Choi

Inventor： Qunhua Wang ,  Weijie Wang ,  Young Jin Choi ,  Seon-Mee Cho ,  Yi Cui ,  Beom Soo Park ,  Soo Young Choi

IPC: H01L29/10 ,  H01L29/12 ,  H01L21/316 ,  H01L29/786 ,  H01L21/31 ,  H01L21/02 ,  C23C16/24 ,  C23C16/34 ,  C23C16/40 ,  C23C16/505 ,  C23C16/56 ,  H01L29/66 ,  H01L21/77

CPC classification number: H01L21/31 ,  C23C16/24 ,  C23C16/345 ,  C23C16/401 ,  C23C16/505 ,  C23C16/56 ,  H01L21/02422 ,  H01L21/02425 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/02675 ,  H01L29/66757 ,  H01L29/786 ,  H01L29/7869 ,  H01L2021/775

Abstract: Embodiments of the disclosure generally provide methods of forming a silicon containing layers in TFT devices. The silicon can be used to form the active channel in a LTPS TFT or be utilized as an element in a gate dielectric layer, a passivation layer or even an etch stop layer. The silicon containing layer is deposited by a vapor deposition process whereby an inert gas, such as argon, is introduced along with the silicon precursor. The inert gas functions to drive out weak, dangling silicon-hydrogen bonds or silicon-silicon bonds so that strong silicon-silicon or silicon-oxygen bonds remain to form a substantially hydrogen free silicon containing layer.

Abstract translation: 本公开的实施例通常提供在TFT器件中形成含硅层的方法。 硅可用于在LTPS TFT中形成有源沟道，或者用作栅极介电层，钝化层或甚至蚀刻停止层中的元素。 通过气相沉积工艺沉积含硅层，由此惰性气体如氩气与硅前体一起引入。 惰性气体起到驱除弱的，悬挂的硅 - 氢键或硅 - 硅键的作用，使得强硅硅或硅 - 氧键保留以形成基本上不含氢的含硅层。

公开(公告)号：US09099573B2

公开(公告)日：2015-08-04

申请号：US14485663

申请日：2014-09-12

Applicant: Yeon Woo Seo ,  Jung-Sub Kim ,  Young Jin Choi ,  Denis Sannikov ,  Han Kyu Seong ,  Dae Myung Chun ,  Jae Hyeok Heo

Inventor： Yeon Woo Seo ,  Jung-Sub Kim ,  Young Jin Choi ,  Denis Sannikov ,  Han Kyu Seong ,  Dae Myung Chun ,  Jae Hyeok Heo

IPC: H01L21/00 ,  H01L33/00 ,  H01L33/14 ,  H01L33/24 ,  H01L33/38 ,  H01L33/08 ,  H01L33/20 ,  H01L33/32

CPC classification number: H01L33/24 ,  F21K9/232 ,  F21S41/147 ,  F21S45/43 ,  F21S45/47 ,  F21Y2115/10 ,  H01L33/007 ,  H01L33/0075 ,  H01L33/0079 ,  H01L33/08 ,  H01L33/145 ,  H01L33/18 ,  H01L33/20 ,  H01L33/32 ,  H01L33/38 ,  H01L33/385 ,  H01L33/387 ,  H01L33/44 ,  H01L33/62 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2933/0016 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of manufacturing a light emitting device having a plurality of nano-light emitting structures is provided. The method comprises depositing a first conductivity-type semiconductor material on a substrate to form a base layer. A mask having a plurality of openings is formed on the base layer. The first conductivity-type nitride semiconductor material is deposited in the openings of the mask to form a plurality of nanocores having a main portion bounded by the mask and an exposed tip portion. A current blocking layer is deposited on the tip portion of the nanocores. A portion of the mask is removed to expose the main portion of the nanocore. An active material layer is deposited on the plurality of nanocores. A second conductivity-type nitride semiconductor layer is deposited on the active material layer.

Abstract translation: 提供一种制造具有多个纳米发光结构的发光器件的方法。 该方法包括在衬底上沉积第一导电型半导体材料以形成基底层。 在基层上形成具有多个开口的掩模。 第一导电型氮化物半导体材料沉积在掩模的开口中以形成具有由掩模界定的主要部分和暴露的尖端部分的多个纳米孔。 电流阻挡层沉积在纳米孔的尖端部分上。 去除掩模的一部分以暴露纳米孔的主要部分。 活性物质层沉积在多个纳米孔上。 第二导电型氮化物半导体层沉积在活性材料层上。

公开(公告)号：US08877301B2

公开(公告)日：2014-11-04

申请号：US13153641

申请日：2011-06-06

Applicant: Gaku Furuta ,  Soo Young Choi ,  Young-Jin Choi

Inventor： Gaku Furuta ,  Soo Young Choi ,  Young-Jin Choi

IPC: C23C16/509 ,  C23C16/458 ,  C23C16/455 ,  H01J37/32

CPC classification number: C23C16/4585 ,  C23C16/45565 ,  C23C16/5096 ,  H01J37/32091 ,  H01J37/32568 ,  H01J37/32577 ,  H01J37/32623 ,  H01J37/32697

Abstract: An asymmetrically grounded susceptor used in a plasma processing chamber for chemical vapor deposition onto large rectangular panels supported on and grounded by the susceptor. A plurality of grounding straps are connected between the periphery of the susceptor to the grounded vacuum chamber to shorten the grounding paths for RF electrons. Flexible straps allow the susceptor to vertically move. The straps provide a conductance to ground which is asymmetric around the periphery. The straps may be evenly spaced but have different thicknesses or different shapes or be removed from available grounding point and hence provide different RF conductances. The asymmetry is selected to improve the deposition uniformity and other qualities of the PECVD deposited film.

Abstract translation: 用于等离子体处理室中的不对称接地的基座，用于化学气相沉积到由基座支撑并接地的大矩形面板上。 多个接地带连接在基座的外围与接地的真空室之间，以缩短RF电子的接地路径。 柔性带允许基座垂直移动。 带子提供对周边不对称的地面电导。 带可以是均匀间隔的，但是具有不同的厚度或不同的形状，或者从可用的接地点去除并因此提供不同的RF电导。 选择不对称性以改善PECVD沉积膜的沉积均匀性和其他质量。

公开(公告)号：US20140117566A1

公开(公告)日：2014-05-01

申请号：US13763927

申请日：2013-02-11

Applicant: Jay-Bok CHOI ,  Kyu-Hyun LEE ,  Mi-Jeong JANG ,  Young-Jin CHOI ,  Ju-Young HUH

Inventor： Jay-Bok CHOI ,  Kyu-Hyun LEE ,  Mi-Jeong JANG ,  Young-Jin CHOI ,  Ju-Young HUH

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10847 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a plurality of parallel-trenches that are parallel to each other, a plurality of intersect-trenches that are parallel to each other, a plurality of active regions that are confined by the parallel-trenches and the intersect-trenches, a plurality of lower conductive lines that cross the active regions, a plurality of upper conductive lines that are parallel to each other, that cross the lower conductive lines, and that cross over the active regions, and data storage elements connected to the active regions. Each of the parallel-trenches and the intersect-trenches is a straight line. The parallel-trenches cross the upper conductive lines and form a first acute angle with the upper conductive lines. The intersect-trenches cross the parallel-trenches and form a second acute angle with the parallel-trenches.

Abstract translation: 半导体器件包括彼此平行的多个平行沟槽，彼此平行的多个相交沟槽，由平行沟槽和交叉沟槽约束的多个有源区域，一个 穿过有源区的多个下导电线，彼此平行的多个上导线，穿过下导电线，并跨越有源区，以及连接到有源区的数据存储元件。 每个平行沟槽和交叉沟槽都是直线。 平行沟槽穿过上导电线并与上导线形成第一锐角。 交叉沟槽与平行沟槽交叉并与平行沟槽形成第二锐角。

公开(公告)号：US08507393B2

公开(公告)日：2013-08-13

申请号：US13098937

申请日：2011-05-02

Applicant: Jeong Hyun Park ,  Jin Gu Kang ,  Young Jin Choi ,  Jae Gwan Park

Inventor： Jeong Hyun Park ,  Jin Gu Kang ,  Young Jin Choi ,  Jae Gwan Park

IPC: C03C14/00

CPC classification number: H01B3/12 ,  C03C8/02 ,  C03C14/004 ,  C03C2214/20 ,  C04B35/16 ,  C04B35/20 ,  C04B2235/3217 ,  C04B2235/3284 ,  C04B2235/3427 ,  C04B2235/3445 ,  C04B2235/365 ,  C04B2235/77 ,  C04B2235/96

Abstract: Provided is a dielectric ceramic composition comprising: 40-70 wt % of a borosilicate-based glass frit comprising 50-80 mol % of SiO2, 15-20 mol % of B2O3, 0.1-5 mol % of one or more alkali metal oxide selected from Li2O and Na2O, and 0.1-30 mol % of one or more alkaline earth metal oxide selected from MgO, CaO, SrO and ZnO; and 30-60 wt % of a ceramic filler represented by Chemical Formula 1: (Zn1-xMgx)2SiO4  (1) wherein 0≦x≦1. The disclosed low temperature co-fired ceramic (LTCC) composition is sinterable at low temperature, with a relative density of at least 95% in the temperature range of 800-900° C., is capable of minimizing electric loss, with a dielectric constant of 4-7 and a very low dielectric loss, and is applicable from the low-frequency band to the millimeter-wave band of 60 GHz or more.

Abstract translation: 提供一种电介质陶瓷组合物，其包含：40-70重量％的硼硅酸盐基玻璃料，其包含50-80摩尔％的SiO 2，15-20摩尔％的B 2 O 3，0.1-5摩尔％的一种或多种碱金属氧化物 从Li 2 O和Na 2 O，以及0.1-30mol％的一种或多种选自MgO，CaO，SrO和ZnO的碱土金属氧化物; 和30-60重量％的由化学式1表示的陶瓷填料：（Zn1-xMgx）2SiO4（1），其中0≤x≤1。 所公开的低温共烧陶瓷（LTCC）组合物在低温下是可烧结的，在800-900℃的温度范围内相对密度至少为95％，能够最小化电损耗，介电常数 并且具有非常低的介电损耗，并且适用于60GHz以上的低频带至毫米波段。

公开(公告)号：US20130140009A1

公开(公告)日：2013-06-06

申请号：US13722637

申请日：2012-12-20

Applicant: John M. White ,  Soo Young Choi ,  Beom Soo Park ,  Gaku Furuta ,  Young Jin Choi ,  Robin L. Tiner

Inventor： John M. White ,  Soo Young Choi ,  Beom Soo Park ,  Gaku Furuta ,  Young Jin Choi ,  Robin L. Tiner

IPC: F28D7/00

CPC classification number: F28D7/00 ,  C23C16/4405 ,  F28D2021/0078 ,  F28F9/26

Abstract: The present invention generally includes a coupling between components. When igniting a plasma remote from a processing chamber, the reactive gas ions may travel to the processing chamber through numerous components. The reactive gas ions may be quite hot and cause the various components to become very hot and thus, the seals between apparatus components may fail. Therefore, it may be beneficial to cool any metallic components through which the reactive gas ions may travel. However, at the interface between the cooled metallic component and a ceramic component, the ceramic component may experience a temperature gradient sufficient to crack the ceramic material due to the heat of the reactive gas ions and the coolness of the metallic component. Therefore, extending a flange of the metallic component into the ceramic component may lessen the temperature gradient at the interface and reduce cracking of the ceramic component.

公开(公告)号：US08368169B2

公开(公告)日：2013-02-05

申请号：US12897095

申请日：2010-10-04

Applicant: Seunguk Han ,  Satoru Yamada ,  Young Jin Choi

Inventor： Seunguk Han ,  Satoru Yamada ,  Young Jin Choi

IPC: H01L21/70

CPC classification number: H01L21/823481 ,  H01L21/76229 ,  H01L21/823425

Abstract: An example semiconductor device includes a trench formed in a semiconductor substrate to define an active region, a filling dielectric layer provided within the trench, an oxide layer provided between the filling dielectric layer and the trench, a nitride layer provided between the oxide layer and the filling dielectric layer, and a barrier layer provided between the oxide layer and the nitride layer.

Abstract translation: 示例性半导体器件包括形成在半导体衬底中以限定有源区的沟槽，设置在沟槽内的填充介电层，设置在填充介电层和沟槽之间的氧化物层，设置在氧化物层和 填充介电层，以及设置在氧化物层和氮化物层之间的阻挡层。

公开(公告)号：US20120264942A1

公开(公告)日：2012-10-18

申请号：US13296049

申请日：2011-11-14

Applicant: In-Cheol Kang ,  Eung-Yoon Kim ,  Young-Jin Choi

Inventor： In-Cheol Kang ,  Eung-Yoon Kim ,  Young-Jin Choi

IPC: C40B30/02 ,  C07D417/04 ,  C07C49/83

CPC classification number: G01N33/6893 ,  C07C50/32 ,  C07C2602/28 ,  C07D417/04 ,  G01N33/566 ,  G01N33/6845 ,  G01N2333/70557 ,  G01N2500/02 ,  G01N2800/108

Abstract: Provided is a compound found by screening a material for inhibiting an osteopontin, in which the material for inhibiting the osteopontin can increase effectiveness as an excellent material for inhibiting an osteoporosis.

Abstract translation: 提供通过筛选抑制骨桥蛋白的材料而发现的化合物，其中用于抑制骨桥蛋白的材料可以提高作为抑制骨质疏松症的优异材料的有效性。

公开(公告)号：US20120202675A1

公开(公告)日：2012-08-09

申请号：US13098937

申请日：2011-05-02

Applicant: Jeong Hyun PARK ,  Jin Gu KANG ,  Young Jin CHOI ,  Jae Gwan PARK

Inventor： Jeong Hyun PARK ,  Jin Gu KANG ,  Young Jin CHOI ,  Jae Gwan PARK

IPC: C03C14/00

CPC classification number: H01B3/12 ,  C03C8/02 ,  C03C14/004 ,  C03C2214/20 ,  C04B35/16 ,  C04B35/20 ,  C04B2235/3217 ,  C04B2235/3284 ,  C04B2235/3427 ,  C04B2235/3445 ,  C04B2235/365 ,  C04B2235/77 ,  C04B2235/96

Abstract: Provided is a dielectric ceramic composition comprising: 40-70 wt % of a borosilicate-based glass frit comprising 50-80 mol % of SiO2, 15-20 mol % of B2O3, 0.1-5 mol % of one or more alkali metal oxide selected from Li2O and Na2O, and 0.1-30 mol % of one or more alkaline earth metal oxide selected from MgO, CaO, SrO and ZnO; and 30-60 wt % of a ceramic filler represented by Chemical Formula 1: (Zn1-xMgx)2SiO4  (1) wherein 0≦x≦1. The disclosed low temperature co-fired ceramic (LTCC) composition is sinterable at low temperature, with a relative density of at least 95% in the temperature range of 800-900° C., is capable of minimizing electric loss, with a dielectric constant of 4-7 and a very low dielectric loss, and is applicable from the low-frequency band to the millimeter-wave band of 60 GHz or more.

Abstract translation: 提供一种电介质陶瓷组合物，其包含：40-70重量％的硼硅酸盐基玻璃料，其包含50-80摩尔％的SiO 2，15-20摩尔％的B 2 O 3，0.1-5摩尔％的一种或多种碱金属氧化物 从Li 2 O和Na 2 O，以及0.1-30mol％的一种或多种选自MgO，CaO，SrO和ZnO的碱土金属氧化物; 和30-60重量％的由化学式1表示的陶瓷填料：（Zn1-xMgx）2SiO4（1）其中0＆nlE; x＆nlE; 1。 所公开的低温共烧陶瓷（LTCC）组合物在低温下是可烧结的，在800-900℃的温度范围内相对密度至少为95％，能够最小化电损耗，介电常数 并且具有非常低的介电损耗，并且适用于60GHz以上的低频带至毫米波段。

公开(公告)号：US20120040536A1

公开(公告)日：2012-02-16

申请号：US13207315

申请日：2011-08-10

Applicant: Gaku Furuta ,  Soo Young Choi ,  Beom Soo Park ,  Young-jin Choi ,  Omori Kenji

Inventor： Gaku Furuta ,  Soo Young Choi ,  Beom Soo Park ,  Young-jin Choi ,  Omori Kenji

IPC: H01L21/318

CPC classification number: H01L21/0217 ,  C23C16/345 ,  C23C16/4404 ,  H01L21/02274 ,  H01L21/02299

Abstract: Embodiments of the present invention provide methods for depositing a nitrogen-containing material on large-sized substrates disposed in a processing chamber. In one embodiment, a method includes processing a batch of substrates within a processing chamber to deposit a nitrogen-containing material on a substrate from the batch of substrates, and performing a seasoning process at predetermined intervals during processing the batch of substrates to deposit a conductive seasoning layer over a surface of a chamber component disposed in the processing chamber. The chamber component may include a gas distribution plate fabricated from a bare aluminum without anodizing. In one example, the conductive seasoning layer may include amorphous silicon, doped amorphous silicon, doped silicon, doped polysilicon, doped silicon carbide, or the like.

Abstract translation: 本发明的实施方案提供了在设置在处理室中的大尺寸基板上沉积含氮材料的方法。 在一个实施方案中，一种方法包括处理处理室内的一批衬底，以将一批含有底物的含氮材料从该批衬底上沉积，并在处理该批衬底期间以预定间隔进行调味过程以沉积导电 在处理室中设置的腔室部件的表面上的调味层。 腔室部件可以包括由裸铝制成而不阳极氧化的气体分配板。 在一个示例中，导电调味层可以包括非晶硅，掺杂非晶硅，掺杂硅，掺杂多晶硅，掺杂碳化硅等。