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13 条记录 (耗时 0.021 秒)

    Cascaded cure approach to fabricate highly tensile silicon nitride films
    1.
    发明授权
    Cascaded cure approach to fabricate highly tensile silicon nitride films 有权
    级联固化方法制造高拉伸氮化硅膜

    公开(公告)号：US08211510B1

    公开(公告)日：2012-07-03

    申请号：US11897838

    申请日：2007-08-31

    申请人： Bhadri Varadarajan ,  Gengwei Jiang ,  Sirish K. Reddy ,  James S. Sims

    发明人： Bhadri Varadarajan ,  Gengwei Jiang ,  Sirish K. Reddy ,  James S. Sims

    IPC分类号： B05D3/06

    CPC分类号： H01L21/3105 ,  C23C14/0652 ,  C23C16/345 ,  C23C16/56 ,  H01L21/0217 ,  H01L21/0231 ,  H01L29/7843

    摘要： A highly tensile dielectric layer is generated on a heat sensitive substrate while not exceeding thermal budget constraints. Cascaded ultraviolet (UV) irradiation is used to produce highly tensile films to be used, for example, in strained NMOS transistor architectures. Successive UV radiation of equal or shorter wavelengths with variable intensity and duration selectively breaks bonds in the Si—N matrix and minimizes shrinkage and film relaxation. Higher tensile stress than a non-cascaded approach may be obtained.

    摘要翻译： 在热敏基材上产生高度拉伸的介电层，而不超过热预算限制。 使用级联紫外（UV）照射来产生例如在应变NMOS晶体管架构中使用的高拉伸膜。 具有可变强度和持续时间的相等或较短波长的连续紫外线辐射选择性地破坏Si-N基体中的键并使收缩和膜弛豫最小化。 可以获得比非级联方法更高的拉伸应力。

    Cascaded cure approach to fabricate highly tensile silicon nitride films
    2.
    发明授权
    Cascaded cure approach to fabricate highly tensile silicon nitride films 有权
    级联固化方法制造高拉伸氮化硅膜

    公开(公告)号：US08512818B1

    公开(公告)日：2013-08-20

    申请号：US13487051

    申请日：2012-06-01

    申请人： Bhadri Varadarajan ,  Gengwei Jiang ,  Sirish K. Reddy ,  James S. Sims

    发明人： Bhadri Varadarajan ,  Gengwei Jiang ,  Sirish K. Reddy ,  James S. Sims

    IPC分类号： B05D3/06

    CPC分类号： H01L21/3105 ,  C23C14/0652 ,  C23C16/345 ,  C23C16/56 ,  H01L21/0217 ,  H01L21/0231 ,  H01L29/7843

    摘要： A highly tensile dielectric layer is generated on a heat sensitive substrate while not exceeding thermal budget constraints. Cascaded ultraviolet (UV) irradiation is used to produce highly tensile films to be used, for example, in strained NMOS transistor architectures. Successive UV radiation of equal or shorter wavelengths with variable intensity and duration selectively breaks bonds in the Si—N matrix and minimizes shrinkage and film relaxation. Higher tensile stress than a non-cascaded approach may be obtained.

    摘要翻译： 在热敏基材上产生高度拉伸的介电层，而不超过热预算限制。 使用级联紫外（UV）照射来产生例如在应变NMOS晶体管架构中使用的高拉伸膜。 具有可变强度和持续时间的相等或较短波长的连续紫外线辐射选择性地破坏Si-N基体中的键并使收缩和膜弛豫最小化。 可以获得比非级联方法更高的拉伸应力。

    Strained transistor architecture and method
    3.
    发明授权
    Strained transistor architecture and method 有权
    应变晶体管结构和方法

    公开(公告)号：US07041543B1

    公开(公告)日：2006-05-09

    申请号：US10923259

    申请日：2004-08-20

    申请人： Bhadri Varadarajan ,  William W. Crew ,  James S. Sims

    发明人： Bhadri Varadarajan ,  William W. Crew ,  James S. Sims

    IPC分类号： H01I21/336 ,  H01L21/8234

    CPC分类号： H01L29/7842 ,  H01L21/823807 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7843

    摘要： Transistor architectures and fabrication processes generate channel strain without adversely impacting the efficiency of the transistor fabrication process while preserving the material quality and enhancing the performance of the resulting transistor. Transistor strain is generated is NMOS devices using a highly tensile post-salicide silicon nitride capping layer on the source and drain regions. The stress from this capping layer is uniaxially transferred to the NMOS channel through the source-drain regions to create tensile strain in NMOS channel.

    摘要翻译： 晶体管架构和制造工艺产生通道应变，而不会不利地影响晶体管制造工艺的效率，同时保持材料质量并增强所得晶体管的性能。 产生晶体管应变是在源极和漏极区域上使用高度拉伸的自对准硅化物氮化硅覆盖层的NMOS器件。 来自该覆盖层的应力通过源极 - 漏极区域单向转移到NMOS沟道，以在NMOS沟道中产生拉伸应变。

    PMOS transistor with compressive dielectric capping layer
    5.
    发明授权
    PMOS transistor with compressive dielectric capping layer 有权
    具有压电绝缘覆盖层的PMOS晶体管

    公开(公告)号：US07214630B1

    公开(公告)日：2007-05-08

    申请号：US11124443

    申请日：2005-05-06

    申请人： Bhadri N. Varadarajan ,  James S. Sims ,  Akhil Singhal

    发明人： Bhadri N. Varadarajan ,  James S. Sims ,  Akhil Singhal

    IPC分类号： H01L21/31

    CPC分类号： H01L21/3185 ,  C23C16/30 ,  C23C16/56 ,  H01L21/3105 ,  H01L21/3148 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7843

    摘要： A salicide layer is deposited on the source/drain regions of a PMOS transistor. A dielectric capping layer having residual compressive stress is formed on the salicide layer by depositing a plurality of PECVD dielectric sublayers and plasma-treating each sublayer. Compressive stress from the dielectric capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in the PMOS channel. To form a compressive dielectric layer, a deposition reactant mixture containing A1 atoms and A2 atoms is provided in a vacuum chamber. Element A2 is more electronegative than element A1, and A1 atoms have a positive oxidation state and A2 atoms have a negative oxidation state when A1 atoms are bonded with A2 atoms. A deposition plasma is generated by applying HF and LF radio-frequency power to the deposition reactant mixture, and a sublayer of compressive dielectric material is deposited. A post-treatment plasma is generated by applying HF and LF radio-frequency power to a post-treatment gas that does not contain at least one of A1 atoms and A2 atoms. Compressive stress in the dielectric sublayer is increased by treating the sublayer in the post-treatment plasma. Processes of depositing a dielectric sublayer and post-treating the sublayer in plasma are repeated until a desired thickness is achieved. The resulting dielectric layer has residual compressive stress.

    摘要翻译： 硅化物层沉积在PMOS晶体管的源/漏区上。 通过沉积多个PECVD电介质子层并对每个子层进行等离子体处理，在自对准硅层上形成具有残余压应力的电介质覆盖层。 来自介电覆盖层的压缩应力通过源极 - 漏极区域单向转移到PMOS沟道，以在PMOS沟道中产生压缩应变。 为了形成压电介质层，在真空室中提供含有A1原子和A2原子的沉积反应物混合物。 元素A2比元素A1更负电，A1原子具有正的氧化态，当A2原子与A2原子键合时，A2原子具有负的氧化态。 通过对沉积反应物混合物施加HF和LF射频功率来产生沉积等离子体，并且沉积压电介质材料的子层。 通过对不包含A1原子和A2原子中的至少一个的后处理气体施加HF和LF射频功率来产生后处理等离子体。 通过处理后处理等离子体中的子层来增加介电层中的压缩应力。 重复沉积介电子层并对等离子体中的子层进行后处理的工艺，直到实现所需的厚度。 所得到的介电层具有残余压应力。

    CONTOURED SHOWERHEAD FOR IMPROVED PLASMA SHAPING AND CONTROL
    6.
    发明申请
    CONTOURED SHOWERHEAD FOR IMPROVED PLASMA SHAPING AND CONTROL 有权
    用于改进等离子体成型和控制的组合式淋浴

    公开(公告)号：US20130334344A1

    公开(公告)日：2013-12-19

    申请号：US13541595

    申请日：2012-07-03

    申请人： Karl F. Leeser ,  James S. Sims

    发明人： Karl F. Leeser ,  James S. Sims

    IPC分类号： B05B1/14 ,  G06F17/50

    CPC分类号： C23C16/509 ,  B05B1/00 ,  B05B1/14 ,  B05B12/00 ,  C23C16/4412 ,  C23C16/45565 ,  G05B19/41 ,  H01J37/32082 ,  H01J37/32091 ,  H01J37/3244 ,  H01J37/32449 ,  H01J37/32541 ,  H01J37/32568 ,  H01J2237/327 ,  H01J2237/3323 ,  H01J2237/334 ,  H01L21/02274

    摘要： Semiconductor processing chamber showerheads with contoured faceplates, as well as techniques for producing such faceplates, are provided. Data describing deposition rate as a function of gap distance between a reference showerhead faceplate and a reference substrate may be obtained, as well as data describing deposition rate as a function of location on the substrate when the reference showerhead and the reference substrate are in a fixed arrangement with respect to each other. The two data sets may be used to determine offsets from a reference plane associated with the faceplate that determine a contour profile to be used with the faceplate.

    摘要翻译： 提供具有轮廓面板的半导体处理室淋浴头以及用于生产这种面板的技术。 可以获得描述作为参考喷头面板和参考基板之间的间隙距离的函数的沉积速率的数据，以及当参考喷头和参考基板处于固定状态时描述作为基板上的位置的函数的沉积速率的数据 相互排列。 两个数据集可用于确定与面板相关联的参考平面的偏移，该偏移确定与面板一起使用的轮廓轮廓。

    PMOS transistor with compressive dielectric capping layer
    7.
    发明授权
    PMOS transistor with compressive dielectric capping layer 有权
    具有压电绝缘覆盖层的PMOS晶体管

    公开(公告)号：US07327001B1

    公开(公告)日：2008-02-05

    申请号：US11731265

    申请日：2007-03-29

    申请人： Akhil Singhal ,  James S. Sims ,  Bhadri N. Varadarajan

    发明人： Akhil Singhal ,  James S. Sims ,  Bhadri N. Varadarajan

    IPC分类号： H01L29/76

    CPC分类号： H01L21/3185 ,  C23C16/30 ,  C23C16/56 ,  H01L21/3105 ,  H01L21/3148 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7843

    摘要： A salicide layer is deposited on the source/drain regions of a PMOS transistor. A dielectric capping layer having residual compressive stress is formed on the salicide layer by depositing a plurality of PECVD dielectric sublayers and plasma-treating each sublayer. Compressive stress from the dielectric capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in the PMOS channel. To form a compressive dielectric layer, a deposition reactant mixture containing A1 atoms and A2 atoms is provided in a vacuum chamber. Element A2 is more electronegative than element A1, and A1 atoms have a positive oxidation state and A2 atoms have a negative oxidation state when A1 atoms are bonded with A2 atoms. A deposition plasma is generated by applying HF and LF radio-frequency power to the deposition reactant mixture, and a sublayer of compressive dielectric material is deposited. A post-treatment plasma is generated by applying HF and LF radio-frequency power to a post-treatment gas that does not contain at least one of A1 atoms and A2 atoms. Compressive stress in the dielectric sublayer is increased by treating the sublayer in the post-treatment plasma. Processes of depositing a dielectric sublayer and post-treating the sublayer in plasma are repeated until a desired thickness is achieved. The resulting dielectric layer has residual compressive stress.

    摘要翻译： 硅化物层沉积在PMOS晶体管的源/漏区上。 通过沉积多个PECVD电介质子层并对每个子层进行等离子体处理，在自对准硅层上形成具有残余压应力的电介质覆盖层。 来自介电覆盖层的压缩应力通过源极 - 漏极区域单向转移到PMOS沟道，以在PMOS沟道中产生压缩应变。 为了形成压电介质层，在真空室中提供含有A1原子和A2原子的沉积反应物混合物。 元素A2比元素A1更负电，A1原子具有正的氧化态，当A2原子与A2原子键合时，A2原子具有负的氧化态。 通过对沉积反应物混合物施加HF和LF射频功率来产生沉积等离子体，并且沉积压电介质材料的子层。 通过对不包含A1原子和A2原子中的至少一个的后处理气体施加HF和LF射频功率来产生后处理等离子体。 通过处理后处理等离子体中的子层来增加介电层中的压缩应力。 重复沉积介电子层并对等离子体中的子层进行后处理的工艺，直到实现所需的厚度。 所得到的介电层具有残余压应力。