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    Method of encapsulating packaged microelectronic devices with a barrier
    7.
    发明授权
    Method of encapsulating packaged microelectronic devices with a barrier 有权
    封装具有屏障的封装微电子器件的方法

    公开(公告)号：US07332376B2

    公开(公告)日：2008-02-19

    申请号：US11516455

    申请日：2006-09-05

    申请人： Chad A. Cobbley

    发明人： Chad A. Cobbley

    IPC分类号： H01L21/48 ,  H01L23/48 ,  H05K3/30

    CPC分类号： H01L23/3121 ,  H01L21/565 ,  H01L23/13 ,  H01L23/4985 ,  H01L24/48 ,  H01L24/83 ,  H01L2224/4824 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  Y10T29/49146 ,  Y10T29/49171 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： Methods and apparatuses for encapsulating a microelectronic die or other components in the fabrication of packaged microelectronic devices. In one aspect of the invention, a packaged microelectronic device assembly includes a microelectronic die, a substrate attached to the die, a protective casing covering a portion of the substrate, and a barrier projecting away from the surface of the substrate. The microelectronic die can have an integrated circuit and a plurality of bond-pads operatively coupled to the integrated circuit. The substrate can have a cap-zone defined by an area that is to be covered by the protective casing, a plurality of contact elements arranged in the cap-zone, a plurality of ball-pads arranged in a ball-pad array outside of the cap-zone, and a plurality of conductive lines coupling the contact elements to the ball-pads. The contact elements are electrically coupled to corresponding bond-pads on the microelectronic die, and the protective casing covers the cap-zone. The barrier on the surface of the substrate is configured so that at least a portion of the barrier is outside of the cap-zone and adjacent to at least a portion of the molded section. The barrier is a seal that inhibits the thermosetting material of the protective casing from covering a portion of the substrate outside of the cap-zone. As such, the barrier prevents thermosetting material from leaking between the substrate and a mold outside of the cap-zone during a molding process.

    摘要翻译： 用于将微电子管芯或其他部件封装在封装的微电子器件的制造中的方法和装置。 在本发明的一个方面，封装的微电子器件组件包括微电子管芯，连接到管芯的衬底，覆盖衬底的一部分的保护壳体以及远离衬底的表面突出的阻挡层。 微电子管芯可以具有集成电路和可操作地耦合到集成电路的多个接合焊盘。 衬底可以具有由被保护壳体覆盖的区域限定的帽区域，布置在帽区域中的多个接触元件，布置在球垫阵列外部的球垫阵列中的多个球垫 帽区，以及将接触元件耦合到球垫的多个导线。 接触元件电耦合到微电子管芯上的相应接合焊盘，并且保护套管覆盖盖区。 衬底表面上的阻挡层被构造成使得阻挡层的至少一部分在帽区域的外部并且与模制部分的至少一部分相邻。 阻挡层是抑制保护壳体的热固性材料在盖帽区域外部覆盖基底的一部分的密封件。 因此，在模制过程中，屏障防止热固性材料在盖区之外的基板和模具之间泄漏。

    Method for packaging flip-chip semiconductor assemblies
    10.
    发明授权
    Method for packaging flip-chip semiconductor assemblies 失效
    封装倒装芯片半导体组件的方法

    公开(公告)号：US07074648B2

    公开(公告)日：2006-07-11

    申请号：US10714188

    申请日：2003-11-14

    申请人： Chad A. Cobbley ,  John VanNortwick ,  Bret K. Street ,  Tongbi Jiang

    发明人： Chad A. Cobbley ,  John VanNortwick ,  Bret K. Street ,  Tongbi Jiang

    IPC分类号： H01L21/44 ,  H01L21/48 ,  H01L21/50

    CPC分类号： G01R1/0483 ,  Y10T29/4913 ,  Y10T29/49144

    摘要： Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

    摘要翻译： 每个包括集成电路（IC）裸片和相关衬底的倒装芯片半导体组件在封装之前使用在线或原位测试插座或芯片附着站的探针进行电测试。 在通过将集成电路（IC）芯片压在基板上的互连点以进行电连接的环氧树脂固化之前，可以测试使用“湿”快速固化环氧树脂进行芯片附接的那些组件，而使用“干”环氧树脂的那些组件 在测试之前进行治愈。 在任一种情况下，骰子或骰子与基板之间的互连中的任何故障都可以很容易地固定，并且消除了在维修期间使用已知好模具（KGD）返工程序的需要。