公开(公告)号：US09679836B2

公开(公告)日：2017-06-13

申请号：US13298102

申请日：2011-11-16

Applicant: Ching-Wen Hsiao ,  Ming-Da Cheng ,  Chih-Wei Lin ,  Chen-Shien Chen ,  Chih-Hua Chen ,  Chen-Cheng Kuo

Inventor： Ching-Wen Hsiao ,  Ming-Da Cheng ,  Chih-Wei Lin ,  Chen-Shien Chen ,  Chih-Hua Chen ,  Chen-Cheng Kuo

IPC: H01L23/48 ,  H01L23/498 ,  H01L21/683 ,  H01L25/10 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/105 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/014 ,  H01L2924/00

Abstract: A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A solder region is disposed in the polymer region and electrically coupled to the redistribution line. The solder region includes a second flat top surface not higher than the first flat top surface.

公开(公告)号：US08659170B2

公开(公告)日：2014-02-25

申请号：US12905276

申请日：2010-10-15

Applicant: Chen-Cheng Kuo ,  Tzuan-Horng Liu ,  Chen-Shien Chen

Inventor： Chen-Cheng Kuo ,  Tzuan-Horng Liu ,  Chen-Shien Chen

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/44

CPC classification number: H01L24/06 ,  H01L21/76838 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/0501 ,  H01L2224/0502 ,  H01L2224/05085 ,  H01L2224/05099 ,  H01L2224/0556 ,  H01L2224/05599 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/15787 ,  H01L2224/13099 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A semiconductor device includes at least two conductive pads, one of the conductive pads being formed above another of the at least two conductive pads, and a redistribution layer extending from at least one of the conductive pads. The semiconductor device also includes a bump structure formed over the conductive pads and electrically coupled to the conductive pads.

Abstract translation: 半导体器件包括至少两个导电焊盘，其中一个导电焊盘形成在至少两个导电焊盘的另一个之上，以及从至少一个导电焊盘延伸的再分配层。 半导体器件还包括形成在导电焊盘上并且电耦合到导电焊盘的凸块结构。

公开(公告)号：US08456008B2

公开(公告)日：2013-06-04

申请号：US13233626

申请日：2011-09-15

Applicant: Chen-Cheng Kuo ,  Kai-Ming Ching ,  Chen Chen-Shien

Inventor： Chen-Cheng Kuo ,  Kai-Ming Ching ,  Chen Chen-Shien

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/81894 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00

Abstract: An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a top inter-metal dielectric (IMD); an opening penetrating the interconnect structure into the semiconductor substrate; a conductor in the opening; and an isolation layer having a vertical portion and a horizontal portion physically connected to each other. The vertical portion is on sidewalls of the opening. The horizontal portion is directly over the interconnect structure. The integrated circuit structure is free from passivation layers vertically between the top IMD and the horizontal portion of the isolation layer.

公开(公告)号：US20130119539A1

公开(公告)日：2013-05-16

申请号：US13298102

申请日：2011-11-16

Applicant: Ching-Wen Hsiao ,  Ming-Da Cheng ,  Chih-Wei Lin ,  Chen-Shien Chen ,  Chih-Hua Chen ,  Chen-Cheng Kuo

Inventor： Ching-Wen Hsiao ,  Ming-Da Cheng ,  Chih-Wei Lin ,  Chen-Shien Chen ,  Chih-Hua Chen ,  Chen-Cheng Kuo

IPC: H05K1/11 ,  H01L21/60 ,  H01L23/485

CPC classification number: H01L23/49816 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/105 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/18161 ,  H01L2924/014 ,  H01L2924/00

Abstract: A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A solder region is disposed in the polymer region and electrically coupled to the redistribution line. The solder region includes a second flat top surface not higher than the first flat top surface.

Abstract translation: 一种装置包括再分布线，以及在再分配线上模制的聚合物区域。 聚合物区域包括第一平坦顶表面。 焊料区域设置在聚合物区域中并电耦合到再分配线路。 焊料区域包括不高于第一平坦顶表面的第二平坦顶表面。

公开(公告)号：US08193639B2

公开(公告)日：2012-06-05

申请号：US12750468

申请日：2010-03-30

Applicant: Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

Inventor： Tzuan-Horng Liu ,  Shang-Yun Hou ,  Shin-Puu Jeng ,  Wei-Cheng Wu ,  Hsiu-Ping Wei ,  Chih-Hua Chen ,  Chen-Cheng Kuo ,  Chen-Shien Chen ,  Ming Hung Tseng

IPC: H01L23/485

CPC classification number: H01L23/585 ,  H01L23/552 ,  H01L23/562 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05012 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/1147 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13147 ,  H01L2224/13655 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

Abstract: An integrated circuit structure includes a semiconductor chip, a metal pad at a major surface of the semiconductor chip, and an under-bump metallurgy (UBM) over and contacting the metal pad. A metal bump is formed over and electrically connected to the UBM. A dummy pattern is formed at a same level, and formed of a same metallic material, as the metal pad.

Abstract translation: 集成电路结构包括半导体芯片，在半导体芯片的主表面处的金属焊盘和在凸块下金属（UBM）上并与金属焊盘接触的集成电路结构。 金属凸块形成在UBM上并与UBM电连接。 在同一水平上形成虚拟图案，并由与金属垫相同的金属材料形成。

公开(公告)号：US20120001334A1

公开(公告)日：2012-01-05

申请号：US13233626

申请日：2011-09-15

Applicant: Chen-Cheng Kuo ,  Kai-Ming Ching ,  Chen Chen-Shien

Inventor： Chen-Cheng Kuo ,  Kai-Ming Ching ,  Chen Chen-Shien

IPC: H01L23/538 ,  H01L23/532

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/81894 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00

Abstract: An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a top inter-metal dielectric (IMD); an opening penetrating the interconnect structure into the semiconductor substrate; a conductor in the opening; and an isolation layer having a vertical portion and a horizontal portion physically connected to each other. The vertical portion is on sidewalls of the opening. The horizontal portion is directly over the interconnect structure. The integrated circuit structure is free from passivation layers vertically between the top IMD and the horizontal portion of the isolation layer.

Abstract translation: 集成电路结构包括半导体衬底; 在所述半导体衬底上的互连结构，其中所述互连结构包括顶部金属间电介质（IMD）; 穿过所述互连结构进入所述半导体衬底的开口; 开幕式的指挥; 以及具有彼此物理连接的垂直部分和水平部分的隔离层。 垂直部分位于开口的侧壁上。 水平部分直接在互连结构上方。 集成电路结构在顶部IMD和隔离层的水平部分之间垂直地没有钝化层。

公开(公告)号：US20110291262A1

公开(公告)日：2011-12-01

申请号：US12789696

申请日：2010-05-28

Applicant: Wen-Wei Shen ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Ming-Fa Chen ,  Rung-De Wang

Inventor： Wen-Wei Shen ,  Chen-Shien Chen ,  Chen-Cheng Kuo ,  Ming-Fa Chen ,  Rung-De Wang

IPC: H01L23/498 ,  B32B3/10 ,  B32B15/04 ,  B32B3/30

CPC classification number: H01L24/16 ,  H01L23/3157 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/03614 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/05023 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/1146 ,  H01L2224/11823 ,  H01L2224/11831 ,  H01L2224/1191 ,  H01L2224/13005 ,  H01L2224/13018 ,  H01L2224/13019 ,  H01L2224/13076 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/1369 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2224/81345 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/05042 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/35 ,  Y10T428/12361 ,  Y10T428/12396 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/206 ,  H01L2224/05552

Abstract: A device includes a work piece including a metal bump; and a dielectric layer having a portion directly over the metal bump. The metal bump and a surface of the portion of the dielectric layer form an interface. A metal finish is formed over and contacting the metal bump. The metal finish extends from over the dielectric layer to below the interface.

Abstract translation: 一种装置包括：包括金属凸块的工件; 以及具有直接在金属凸块上的部分的介电层。 金属凸块和电介质层部分的表面形成界面。 在金属凸块上方形成金属涂层并与金属凸块接触。 金属表面从介电层上延伸到界面的下方。

公开(公告)号：US07843064B2

公开(公告)日：2010-11-30

申请号：US12152381

申请日：2008-05-14

Applicant: Chen-Cheng Kuo ,  Kai-Ming Ching ,  Chen Chen-Shien

Inventor： Chen-Cheng Kuo ,  Kai-Ming Ching ,  Chen Chen-Shien

IPC: H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/13009 ,  H01L2224/13099 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/81894 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01068 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/00

Abstract: An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a top inter-metal dielectric (IMD); an opening penetrating the interconnect structure into the semiconductor substrate; a conductor in the opening; and an isolation layer having a vertical portion and a horizontal portion physically connected to each other. The vertical portion is on sidewalls of the opening. The horizontal portion is directly over the interconnect structure. The integrated circuit structure is free from passivation layers vertically between the top IMD and the horizontal portion of the isolation layer.

Abstract translation: 集成电路结构包括半导体衬底; 在所述半导体衬底上的互连结构，其中所述互连结构包括顶部金属间电介质（IMD）; 穿过所述互连结构进入所述半导体衬底的开口; 开幕式的指挥; 以及具有彼此物理连接的垂直部分和水平部分的隔离层。 垂直部分位于开口的侧壁上。 水平部分直接在互连结构上方。 集成电路结构在顶部IMD和隔离层的水平部分之间垂直地没有钝化层。

公开(公告)号：US07785927B2

公开(公告)日：2010-08-31

申请号：US12392918

申请日：2009-02-25

Applicant: Chen-Shien Chen ,  Kai-Ming Ching ,  Chih-Hua Chen ,  Chen-Cheng Kuo

Inventor： Chen-Shien Chen ,  Kai-Ming Ching ,  Chih-Hua Chen ,  Chen-Cheng Kuo

IPC: H01L21/98

CPC classification number: H01L25/0657 ,  H01L21/563 ,  H01L21/6835 ,  H01L21/76898 ,  H01L24/02 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/50 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04073 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/2518 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83102 ,  H01L2224/83855 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H01L2924/0665 ,  H01L2924/00 ,  H01L2224/48145 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A semiconductor die package is provided. The semiconductor die package includes a plurality of dies arranged in a stacked configuration. Through-silicon vias are formed in the lower or intermediate dies to allow electrical connections to dies stacked above. The lower die is positioned face up and has redistribution lines electrically coupling underlying semiconductor components to the through-silicon vias. The dies stacked above the lower die may be oriented face up such that the contact pads are facing away from the lower die or flipped such that the contact pads are facing the lower die. The stacked dies may be electrically coupled to the redistribution lines via wire bonding or solder balls. Additionally, the lower die may have another set of redistribution lines on an opposing side from the stacked dies to reroute the vias to a different pin-out configuration.

Abstract translation: 提供半导体管芯封装。 半导体管芯封装包括以堆叠构造布置的多个管芯。 在下部或中间模具中形成通孔，以允许电连接到上面堆叠的管芯。 下模具面向上放置并具有将下面的半导体部件电耦合到通硅通孔的再分配线。 堆叠在下模具上方的模具可以朝上取向，使得接触焊盘背离下模或翻转，使得接触焊盘面向下模。 堆叠的管芯可以通过引线接合或焊球电耦合到再分配线。 此外，下模具可以在与堆叠的管芯相对的一侧上具有另一组重新分布线，以将通孔重新路由到不同的引脚配置。

公开(公告)号：US20090269905A1

公开(公告)日：2009-10-29

申请号：US12495124

申请日：2009-06-30

Applicant: Chen-Shien Chen ,  Chen-Cheng Kuo ,  Kai-Ming Ching ,  Chih-Hua Chen

Inventor： Chen-Shien Chen ,  Chen-Cheng Kuo ,  Kai-Ming Ching ,  Chih-Hua Chen

IPC: H01L21/762 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit structure includes a substrate; a through-silicon via (TSV) in the substrate, the TSV being tapered; a hard mask region extending from a top surface of the substrate into the substrate, wherein the hard mask encircles a top portion of the TSV; dielectric layers over the substrate; and a metal post extending from a top surface of the dielectric layers to the TSV, wherein the metal post comprises same materials as the TSV.

Abstract translation: 集成电路结构包括：基板; 在衬底中的穿硅通孔（TSV），TSV是锥形的; 从所述基板的顶表面延伸到所述基板中的硬掩模区域，其中所述硬掩模围绕所述TSV的顶部; 衬底上的介电层; 以及从电介质层的顶表面延伸到TSV的金属柱，其中金属柱包括与TSV相同的材料。