公开(公告)号：US07346982B2

公开(公告)日：2008-03-25

申请号：US11086642

申请日：2005-03-22

申请人： Chong Ho Kim ,  Dong Kuk Kim ,  Hyo Soo Lee ,  Young Hwan Shin

发明人： Chong Ho Kim ,  Dong Kuk Kim ,  Hyo Soo Lee ,  Young Hwan Shin

IPC分类号： H05K3/02

CPC分类号： H05K3/4682 ,  H05K3/0097 ,  H05K3/205 ,  H05K3/28 ,  H05K2201/0355 ,  H05K2203/054 ,  H05K2203/1536 ,  Y10T29/49126 ,  Y10T29/49156 ,  Y10T29/49163 ,  Y10T29/49165 ,  Y10T428/24917 ,  Y10T428/24926

摘要： A method is directed towards fabricating a printed circuit board (PCB) having a thin core layer. In the method, a substrate, where a copper foil is formed on a release film and a prepreg, is employed as a base substrate and a core insulating layer is removed after the fabrication of the PCB, thereby reducing the thickness of the final product.

摘要翻译： 一种方法涉及制造具有薄芯层的印刷电路板（PCB）。 在该方法中，在剥离膜和预浸料坯上形成铜箔的基板被用作基底基板，并且在PCB的制造之后去除芯绝缘层，从而减小最终产品的厚度。

公开(公告)号：US07629692B2

公开(公告)日：2009-12-08

申请号：US11484708

申请日：2006-07-12

申请人： Chong Ho Kim ,  Jong Min Choi ,  Young Hwan Shin

发明人： Chong Ho Kim ,  Jong Min Choi ,  Young Hwan Shin

IPC分类号： H01L21/00

CPC分类号： H05K3/428 ,  H05K3/064 ,  H05K2201/09545 ,  H05K2203/0542 ,  H05K2203/1394 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A via hole having a fine hole land includes a first conductive layer formed on an inner wall of the via hole, the first conductive layer being in contact with a hole formed in an insulation layer and extendedly projected to the outside and having the same diameter as the hole in the insulation layer; a second conductive layer contacted with the first conductive layer and formed on an inner wall thereof and projected to the outside and having the same height as the first conductive layer; and a circuit line, formed on the insulation layer, to connect the first conductive layer extendedly projected to the outside of hole in the insulation layer, where the second conductive layer has the same height as the first conductive layer and the fine hole land is connected to wire bonding pad or solder ball pad through the circuit line.

摘要翻译： 具有细孔面的通孔包括形成在通孔的内壁上的第一导电层，第一导电层与形成在绝缘层中的孔相接触并且向外延伸并且具有与 绝缘层中的孔; 第二导电层，与第一导电层接触并形成在其内壁上并且突出到外部并具有与第一导电层相同的高度; 以及电路线，形成在所述绝缘层上，以将所述第一导电层与所述绝缘层中的孔的外部延伸地连接，其中所述第二导电层具有与所述第一导电层相同的高度，并且所述细孔平台被连接 通过电路线焊接焊盘或焊球焊盘。

公开(公告)号：US20080209722A1

公开(公告)日：2008-09-04

申请号：US12068457

申请日：2008-02-06

申请人： Chong Ho Kim ,  Jong Min Choi ,  Young Hwan Shin

发明人： Chong Ho Kim ,  Jong Min Choi ,  Young Hwan Shin

IPC分类号： H05K3/42 ,  H05K3/10

CPC分类号： H05K3/428 ,  H05K3/064 ,  H05K2201/09545 ,  H05K2203/0542 ,  H05K2203/1394 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A method for forming a via hole having a fine hole land with which the density of circuit patterns can be increased. The method includes forming a via hole in a copper clad laminate, coating an etching resist over the copper clad laminate, and forming a circuit pattern on the copper foil of the copper clad laminate; forming a seed layer, coating a photoresist, and exposing an inner wall of the via hole; and forming a plated layer on the inner wall of the via hole and removing the photoresist and the seed layer.

摘要翻译： 一种用于形成通孔的方法，该通孔具有能够增加电路图案的密度的细小空隙区域。 该方法包括在覆铜层压板中形成通孔，在覆铜层压板上涂覆抗蚀剂，并在覆铜层压板的铜箔上形成电路图案; 形成种子层，涂覆光致抗蚀剂，并暴露通孔的内壁; 在通孔的内壁上形成镀层，除去光致抗蚀剂和种子层。

公开(公告)号：US20110095421A1

公开(公告)日：2011-04-28

申请号：US12926137

申请日：2010-10-27

申请人： Ey Yong Kim ,  Young Hwan Shin ,  Soon Jin Cho ,  Jong Yong Kim ,  Jin Seok Lee

发明人： Ey Yong Kim ,  Young Hwan Shin ,  Soon Jin Cho ,  Jong Yong Kim ,  Jin Seok Lee

IPC分类号： H01L23/498 ,  H01L21/60

CPC分类号： H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/31 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2224/83051 ,  H01L2224/92125 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/00012 ,  H01L2924/00

摘要： There is provided a flip chip package including an electronic device, a board including a conductive pad disposed inside a mounting region of the board on which the electronic device is mounted, and a connection pad disposed outside the mounting region, a resin layer formed on the board and including a trench formed by removing a part of the resin layer, and a dam member provided on the trench and preventing the leakage of an underfill between the mounting region and the connection pad. Since the dam member, formed on the processed resin layer, can prevent the leakage of the underfill, a package defect rate can be lowered, and connection reliability can be improved.

摘要翻译： 提供了一种倒装芯片封装，包括电子器件，包括设置在其上安装有电子器件的板的安装区域内的导电焊盘的基板和设置在安装区域外部的连接焊盘，形成在其上的树脂层 并且包括通过去除树脂层的一部分而形成的沟槽，以及设置在沟槽上的防止构件，并防止在安装区域和连接衬垫之间的底部填充物的泄漏。 由于形成在加工树脂层上的阻挡部件能够防止底部填充物的泄漏，因此能够降低包装缺陷率，可以提高连接可靠性。

公开(公告)号：US20080223610A1

公开(公告)日：2008-09-18

申请号：US12116679

申请日：2008-05-07

申请人： Jae Min Choi ,  Young Hwan Shin

发明人： Jae Min Choi ,  Young Hwan Shin

IPC分类号： H01R12/04

CPC分类号： H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/19043 ,  H05K1/113 ,  H05K3/4614 ,  H05K3/4623 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/10378 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： Disclosed is a ball grid array (BGA) package substrate, in which a wire bonding pad and a solder ball pad are formed on a via hole, making high freedom in design of a circuit pattern and a high density circuit pattern possible, and a method of fabricating the same.

摘要翻译： 公开了一种球栅阵列（BGA）封装基板，其中引线接合焊盘和焊球焊盘形成在通孔上，使电路图案的设计和高密度电路图案具有高自由度，以及方法 的制造。

公开(公告)号：US06405431B1

公开(公告)日：2002-06-18

申请号：US09467780

申请日：1999-12-20

申请人： Dong Shin ,  Keon Yang Park ,  Young Hwan Shin ,  Byung Kook Sun ,  Jae Heun Joung

发明人： Dong Shin ,  Keon Yang Park ,  Young Hwan Shin ,  Byung Kook Sun ,  Jae Heun Joung

IPC分类号： H01K310

CPC分类号： H05K3/4652 ,  H05K3/0035 ,  H05K3/0038 ,  H05K2201/0358 ,  H05K2201/09518 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

摘要： A method for manufacturing a build-up multi-layer printed circuit board is disclosed in which a YAG laser is used upon the formation of a via hole in the multi-layer printed circuit board, such that it can have the following advantages: the manufacturing process would become simple; the component packaging density and freedom for the design of the board would be improved; and a high speed of signal process would be ensured. The method for manufacturing a build-up multi-layer printed circuit board includes the steps of: forming a first printed circuit pattern on a copper clad laminate (CCL) by applying a general photo-etching process, the CCL having a copper foil on the one face thereof; stacking a resin-coated (on one face) copper foil (RCC) on the CCL with the first printed circuit pattern formed thereon, and heating and pressing this structure; irradiating a YAG laser to the board with said RCC stacked so as to form a via hole at a predetermined position by removing said RCC; carrying out an electroless and electro copper plating on the board with the via hole formed therein to form a plated layer; and forming a second printed circuit pattern on said plated layer to electrically connect the layers on which the first and second printed circuit patterns are formed.

摘要翻译： 公开了一种用于制造积层多层印刷电路板的方法，其中在多层印刷电路板中形成通孔时使用YAG激光器，使得其可以具有以下优点：制造 过程变得简单; 组件封装密度和板的设计自由度将得到改善; 并且可以确保信号处理的高速度。 用于制造积层多层印刷电路板的方法包括以下步骤：通过施加一般的光蚀刻工艺在覆铜层压板（CCL）上形成第一印刷电路图案，将具有铜箔的CCL 一面; 在其上形成有第一印刷电路图案的CCL上堆叠树脂涂覆（一面）铜箔（RCC），并加热并压制该结构; 用所述RCC将YAG激光照射到所述板上，以便通过去除所述RCC在预定位置形成通孔; 在其上形成有通孔的板上进行化学镀和电镀铜以形成镀层; 以及在所述镀层上形成第二印刷电路图案，以电连接形成有第一和第二印刷电路图案的层。

公开(公告)号：US09161460B2

公开(公告)日：2015-10-13

申请号：US13308439

申请日：2011-11-30

申请人： Hyung Gi Ha ,  Jae Won Jung ,  Yong Hwan Kim ,  Jong Jin Lee ,  Ja Ho Koo ,  Young Hwan Shin ,  Dong Kyu Lee

发明人： Hyung Gi Ha ,  Jae Won Jung ,  Yong Hwan Kim ,  Jong Jin Lee ,  Ja Ho Koo ,  Young Hwan Shin ,  Dong Kyu Lee

IPC分类号： H05K1/02 ,  H05K1/03 ,  H05K3/38 ,  H05K3/46 ,  H05K1/11

CPC分类号： H05K1/09 ,  H05K1/0284 ,  H05K1/11 ,  H05K3/383 ,  H05K3/385 ,  H05K3/462 ,  H05K2201/0195 ,  H05K2201/0239

摘要： Disclosed herein are a printed circuit board and a method for manufacturing the same. The printed circuit board includes: a base substrate having a metal pattern for a circuit; and a surface roughness provided on the metal pattern, wherein the surface roughness has a first surface roughness in an anchor structure and a second surface roughness having a black oxide layer in a needle structure formed on the first surface roughness.

摘要翻译： 这里公开了一种印刷电路板及其制造方法。 印刷电路板包括：具有用于电路的金属图案的基底基板; 以及设置在所述金属图案上的表面粗糙度，其中所述表面粗糙度在锚结构中具有第一表面粗糙度，以及在所述第一表面粗糙度上形成的针结构中具有黑色氧化物层的第二表面粗糙度。

公开(公告)号：US20100261348A1

公开(公告)日：2010-10-14

申请号：US12801723

申请日：2010-06-22

申请人： Kyoung Ro Yoon ,  Young Hwan Shin ,  Yoon Su Kim ,  Tae Gon Lee

发明人： Kyoung Ro Yoon ,  Young Hwan Shin ,  Yoon Su Kim ,  Tae Gon Lee

IPC分类号： H01L21/768

CPC分类号： H01L23/49838 ,  H01L21/4846 ,  H01L23/49816 ,  H01L2924/0002 ,  H05K1/0265 ,  H05K3/06 ,  H05K3/243 ,  H05K3/28 ,  H05K3/427 ,  H05K2201/0352 ,  H05K2201/09736 ,  H05K2203/0369 ,  H01L2924/00

摘要： A method for fabricating a semiconductor package substrate, including: preparing a copper clad laminate and half etching a copper foil on a wire bonding pad side of the copper clad laminate; depositing a first etching resist on the opposite sides of the copper clad laminate; forming circuit patterns on the first etching resist, constructing circuits including a wire bonding pad and a ball pad after the model of the circuit patterns, and removing the first etching resist; applying a solder resist to the copper clad laminate in such a way to expose the wire bonding pad and the ball pad; and plating the wire bonding pad with gold and subjecting the ball pad to surface treatment.

摘要翻译： 一种半导体封装基板的制造方法，其特征在于，包括：在覆铜层压板的引线接合焊盘侧准备覆铜层压板并半铜蚀刻铜箔; 在覆铜层压板的相对侧上沉积第一蚀刻抗蚀剂; 在所述第一蚀刻抗蚀剂上形成电路图案，在所述电路图案的模型之后构造包括引线接合焊盘和球垫的电路，以及去除所述第一抗蚀剂; 以覆铜层压板的方式涂覆阻焊剂，以使引线接合焊盘和焊盘露出; 并用金焊接引线接合垫，并对球垫进行表面处理。

公开(公告)号：US07768116B2

公开(公告)日：2010-08-03

申请号：US11495649

申请日：2006-07-31

申请人： Kyoung Ro Yoon ,  Young Hwan Shin ,  Yoon Su Kim ,  Tae Gon Lee

发明人： Kyoung Ro Yoon ,  Young Hwan Shin ,  Yoon Su Kim ,  Tae Gon Lee

IPC分类号： H01L23/02

CPC分类号： H01L23/49838 ,  H01L21/4846 ,  H01L23/49816 ,  H01L2924/0002 ,  H05K1/0265 ,  H05K3/06 ,  H05K3/243 ,  H05K3/28 ,  H05K3/427 ,  H05K2201/0352 ,  H05K2201/09736 ,  H05K2203/0369 ,  H01L2924/00

摘要： Disclosed herein are a semiconductor package substrate and a method for fabricating the same. In the semiconductor package substrate, the circuit layer of the wire bonding pad side differs in thickness from that of the ball pad side to which a half etching process is applied. In addition, a connection through hole is constructed to provide an electrical connection between the plating lead lines on the wire bonding pad side and the ball pad side, thereby preventing electrical disconnection when the plating lead line of the wire bonding pad side is cut.

摘要翻译： 本文公开了一种半导体封装基板及其制造方法。 在半导体封装基板中，引线接合焊盘侧的电路层的厚度与施加半蚀刻工序的焊盘侧的厚度不同。 此外，连接通孔被构造成在引线接合焊盘侧的电镀引线和焊盘侧之间提供电连接，从而防止当焊线焊盘侧的电镀引线被切断时的断电。

公开(公告)号：US07387917B2

公开(公告)日：2008-06-17

申请号：US11086625

申请日：2005-03-22

申请人： Jae Min Choi ,  Young Hwan Shin

发明人： Jae Min Choi ,  Young Hwan Shin

IPC分类号： H01L21/00

CPC分类号： H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/19043 ,  H05K1/113 ,  H05K3/4614 ,  H05K3/4623 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/10378 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： Disclosed is a ball grid array (BGA) package substrate, in which a wire bonding pad and a solder ball pad are formed on a via hole, making high freedom in design of a circuit pattern and a high density circuit pattern possible, and a method of fabricating the same.

摘要翻译： 公开了一种球栅阵列（BGA）封装基板，其中引线接合焊盘和焊球焊盘形成在通孔上，使电路图案的设计和高密度电路图案具有高自由度，以及方法 的制造。