公开(公告)号：US20070298585A1

公开(公告)日：2007-12-27

申请号：US11765944

申请日：2007-06-20

申请人： Dmitry Lubomirsky ,  Srinivas Nemani ,  Ellie Yieh

发明人： Dmitry Lubomirsky ,  Srinivas Nemani ,  Ellie Yieh

IPC分类号： H01L21/76

CPC分类号： H01L21/76229

摘要： Methods to reduce film cracking in a dielectric layer are described. The methods may include the steps of depositing a first dielectric film on a substrate and removing a top portion of the first dielectric film by performing an etch on the film. The methods may also include depositing a second dielectric film over the etched first film, and removing a top portion of the second dielectric film. In addition, the methods may include annealing the first and second dielectric films to form the dielectric layer, where the removal of the top portions from the first and the second dielectric films reduces a stress level in the dielectric layer.

摘要翻译： 描述了减少电介质层中的膜破裂的方法。 所述方法可以包括以下步骤：在衬底上沉积第一电介质膜并通过对膜进行蚀刻来去除第一电介质膜的顶部。 所述方法还可以包括在蚀刻的第一膜上沉积第二电介质膜，以及去除第二电介质膜的顶部。 此外，所述方法可以包括退火第一和第二介电膜以形成电介质层，其中从第一和第二电介质膜去除顶部部分降低了介电层中的应力水平。

公开(公告)号：US08232176B2

公开(公告)日：2012-07-31

申请号：US11765944

申请日：2007-06-20

申请人： Dmitry Lubomirsky ,  Srinivas D. Nemani ,  Ellie Yieh

发明人： Dmitry Lubomirsky ,  Srinivas D. Nemani ,  Ellie Yieh

IPC分类号： H01L21/762

CPC分类号： H01L21/76229

摘要： Methods to reduce film cracking in a dielectric layer are described. The methods may include the steps of depositing a first dielectric film on a substrate and removing a top portion of the first dielectric film by performing an etch on the film. The methods may also include depositing a second dielectric film over the etched first film, and removing a top portion of the second dielectric film. In addition, the methods may include annealing the first and second dielectric films to form the dielectric layer, where the removal of the top portions from the first and the second dielectric films reduces a stress level in the dielectric layer.

摘要翻译： 描述了减少电介质层中的膜破裂的方法。 所述方法可以包括以下步骤：在衬底上沉积第一电介质膜并通过对膜进行蚀刻来去除第一电介质膜的顶部。 所述方法还可以包括在蚀刻的第一膜上沉积第二电介质膜，以及去除第二电介质膜的顶部。 此外，所述方法可以包括退火第一和第二介电膜以形成电介质层，其中从第一和第二电介质膜去除顶部部分降低了介电层中的应力水平。

公开(公告)号：US20070289534A1

公开(公告)日：2007-12-20

申请号：US11754858

申请日：2007-05-29

申请人： Dmitry Lubomirsky ,  Qiwei Liang ,  Soonam Park ,  Kien Chuc ,  Ellie Yieh

发明人： Dmitry Lubomirsky ,  Qiwei Liang ,  Soonam Park ,  Kien Chuc ,  Ellie Yieh

IPC分类号： C23C16/452

CPC分类号： C23C16/46 ,  C23C16/452 ,  C23C16/45565 ,  C23C16/45574 ,  H01L21/67115

摘要： A system to form a dielectric layer on a substrate from a plasma of dielectric precursors is described. The system may include a deposition chamber, a substrate stage in the deposition chamber to hold the substrate, and a remote plasma generating system coupled to the deposition chamber, where the plasma generating system is used to generate a dielectric precursor having one or more reactive radicals. The system may also include a radiative heating system to heat the substrate that includes at least one light source, where at least some of the light emitted from the light source travels through the top side of the deposition chamber before reaching the substrate. The system may also include a precursor distribution system to introduce the reactive radical precursor and additional dielectric precursors to the deposition chamber. An in-situ plasma generating system may also be included to generate the plasma in the deposition chamber from the dielectric precursors supplied to the deposition chamber.

摘要翻译： 描述了从电介质前体的等离子体在衬底上形成电介质层的系统。 该系统可以包括沉积室，用于保持衬底的沉积室中的衬底台和耦合到沉积室的远程等离子体生成系统，其中等离子体产生系统用于产生具有一个或多个反应性基团的电介质前体 。 该系统还可以包括辐射加热系统以加热包括至少一个光源的基板，其中从光源发射的至少一些光在到达基板之前穿过沉积室的顶侧。 该系统还可以包括将反应性基团前体和另外的电介质前体引入沉积室的前体分配系统。 还可以包括原位等离子体产生系统，以从沉积室中提供的电介质前体在沉积室中产生等离子体。

公开(公告)号：US20070277734A1

公开(公告)日：2007-12-06

申请号：US11754916

申请日：2007-05-29

申请人： Dmitry Lubomirsky ,  Qiwei Liang ,  Soonam Park ,  Kien Chuc ,  Ellie Yieh

发明人： Dmitry Lubomirsky ,  Qiwei Liang ,  Soonam Park ,  Kien Chuc ,  Ellie Yieh

IPC分类号： C23C16/00

CPC分类号： C23C16/45565 ,  C23C16/402 ,  C23C16/45574 ,  C23C16/505

摘要： A system to form a dielectric layer on a substrate from a plasma of dielectric precursors is described. The system may include a deposition chamber, a substrate stage in the deposition chamber to hold the substrate, and a remote plasma generating system coupled to the deposition chamber, where the plasma generating system is used to generate a dielectric precursor having one or more reactive radicals. The system may also include a precursor distribution system comprising a dual-channel showerhead positioned above the substrate stage. The showerhead may have a faceplate with a first set of openings through which the reactive radical precursor enters the deposition chamber, and a second set of openings through which a second dielectric precursor enters the deposition chamber. An in-situ plasma generating system may also be included to generate the plasma in the deposition chamber from the dielectric precursors supplied to the deposition chamber.

摘要翻译： 描述了从电介质前体的等离子体在衬底上形成电介质层的系统。 该系统可以包括沉积室，用于保持衬底的沉积室中的衬底台和耦合到沉积室的远程等离子体生成系统，其中等离子体产生系统用于产生具有一个或多个反应性基团的电介质前体 。 该系统还可以包括前体分配系统，其包括位于衬底台上方的双通道喷头。 喷头可以具有面板，其具有第一组开口，反应性自由基前体通过该开口进入沉积室，以及第二组开口，第二介电体前体通过该开口进入沉积室。 还可以包括原位等离子体产生系统，以从沉积室中提供的电介质前体在沉积室中产生等离子体。

公开(公告)号：US5963840A

公开(公告)日：1999-10-05

申请号：US748960

申请日：1996-11-13

申请人： Li-Qun Xia ,  Ellie Yieh ,  Srinivas Nemani

发明人： Li-Qun Xia ,  Ellie Yieh ,  Srinivas Nemani

IPC分类号： C23C14/00 ,  C23C16/30 ,  C23C16/40 ,  C23C16/511 ,  H01L21/306 ,  H01L21/31 ,  H01L21/316 ,  H01L21/44

CPC分类号： H01L21/31625 ,  C23C16/401 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02301 ,  H01L21/02312 ,  H01L21/02315 ,  H01L21/0234 ,  H01L21/02362

摘要： The present invention provides systems, methods and apparatus for high temperature (at least about 500-800.degree. C.) processing of semiconductor wafers. The systems, methods and apparatus of the present invention allow multiple process steps to be performed in situ in the same chamber to reduce total processing time and to ensure high quality processing for high aspect ratio devices. Performing multiple process steps in the same chamber also increases the control of the process parameters and reduces device damage. In particular, the present invention can provide high temperature deposition, heating and efficient cleaning for forming dielectric films having thickness uniformity, good gap fill capability, high density, low moisture, and other desired characteristics.

摘要翻译： 本发明提供用于半导体晶片的高温（至少约500-800℃）处理的系统，方法和装置。 本发明的系统，方法和装置允许多个工艺步骤在相同的腔室中原位进行，以减少总处理时间，并确保对高宽比装置的高质量处理。 在同一个室内执行多个工艺步骤也可以增加工艺参数的控制并减少设备损坏。 特别地，本发明可以提供用于形成具有厚度均匀性，良好间隙填充能力，高密度，低湿度和其它所需特性的介电膜的高温沉积，加热和有效清洁。

公开(公告)号：US20170069488A1

公开(公告)日：2017-03-09

申请号：US15356475

申请日：2016-11-18

申请人： Ellie Yieh ,  Ludovic Godet ,  Srinivas Nemani ,  Er-Xuan Ping ,  Gary Dickerson

发明人： Ellie Yieh ,  Ludovic Godet ,  Srinivas Nemani ,  Er-Xuan Ping ,  Gary Dickerson

IPC分类号： H01L21/02 ,  H01L21/285 ,  H01L21/3213 ,  C23C14/02 ,  C23C16/455 ,  C23C16/02 ,  C23C16/04 ,  H01J37/32 ,  C23C16/50 ,  H01L21/311 ,  C23C14/04

CPC分类号： H01L21/02271 ,  C23C14/021 ,  C23C14/046 ,  C23C16/0227 ,  C23C16/045 ,  C23C16/45544 ,  C23C16/50 ,  H01J37/32009 ,  H01J2237/334 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02315 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/31116 ,  H01L21/32136 ,  H01L21/67017 ,  H01L21/67213 ,  H01L21/76224

摘要： Embodiments include methods and systems of 3D structure fill. In one embodiment, a method of filling a trench in a wafer includes performing directional plasma treatment with an ion beam at an angle with respect to a sidewall of the trench to form a treated portion of the sidewall and an untreated bottom of the trench. A material is deposited in the trench. The deposition rate of the material on the treated portion of the sidewall is different than a second deposition rate on the untreated bottom of the trench. In one embodiment, a method includes depositing a material on the wafer, filling a bottom of the trench and forming a layer on a sidewall of the trench and a top surface adjacent to the trench. The method includes etching the layer with an ion beam at an angle with respect to the sidewall.

摘要翻译： 实施例包括3D结构填充的方法和系统。 在一个实施例中，在晶片中填充沟槽的方法包括使用离子束相对于沟槽的侧壁以一定角度执行定向等离子体处理，以形成侧壁的处理部分和沟槽的未处理底部。 材料沉积在沟槽中。 材料在侧壁的处理部分上的沉积速率不同于沟槽的未处理底部上的第二沉积速率。 在一个实施例中，一种方法包括在晶片上沉积材料，填充沟槽的底部并在沟槽的侧壁上形成层，以及邻近沟槽的顶表面。 该方法包括用相对于侧壁成一定角度的离子束蚀刻该层。

公开(公告)号：US06465366B1

公开(公告)日：2002-10-15

申请号：US09660268

申请日：2000-09-12

申请人： Srinivas Nemani ,  Li-Qun Xia ,  Ellie Yieh

发明人： Srinivas Nemani ,  Li-Qun Xia ,  Ellie Yieh

IPC分类号： H01L2131

CPC分类号： H01L21/76829 ,  C23C16/325 ,  C23C16/505 ,  H01L21/0276 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/314 ,  H01L21/7681

摘要： A method for forming a silicon carbide layer for use in integrated circuit fabrication is disclosed. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and an inert gas in the presence of an electric field. The electric field is generated using mixed frequency radio frequency (RF) power. The silicon carbide layer is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the silicon carbide layer is used as a hardmask for fabricating integrated circuit structures such as, for example, a damascene structure. In another integrated circuit fabrication process, the silicon carbide layer is used as an anti-reflective coating (ARC) for DUV lithography.

摘要翻译： 公开了一种用于形成用于集成电路制造的碳化硅层的方法。 通过在电场的存在下使包含硅源，碳源和惰性气体的气体混合物反应来形成碳化硅层。 使用混频射频（RF）功率产生电场。 碳化硅层与集成电路制造工艺兼容。 在一个集成电路制造工艺中，碳化硅层用作用于制造集成电路结构的硬掩模，例如镶嵌结构。 在另一个集成电路制造工艺中，碳化硅层用作用于DUV光刻的抗反射涂层（ARC）。

公开(公告)号：US6114216A

公开(公告)日：2000-09-05

申请号：US746631

申请日：1996-11-13

申请人： Ellie Yieh ,  Li-Qun Xia ,  Srinivas Nemani

发明人： Ellie Yieh ,  Li-Qun Xia ,  Srinivas Nemani

IPC分类号： H01L21/76 ,  C23C16/02 ,  C23C16/40 ,  C23C16/44 ,  C23C16/455 ,  C23C16/458 ,  C23C16/46 ,  C23C16/52 ,  C23C16/54 ,  H01L21/225 ,  H01L21/31 ,  H01L21/316 ,  H01L21/762

CPC分类号： C23C16/45565 ,  C23C16/0245 ,  C23C16/402 ,  C23C16/4405 ,  C23C16/4411 ,  C23C16/4412 ,  C23C16/45561 ,  C23C16/4586 ,  C23C16/46 ,  C23C16/52 ,  C23C16/54 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02301 ,  H01L21/02362 ,  H01L21/2255 ,  H01L21/31612 ,  H01L21/31625

摘要： The present invention provides systems, methods and apparatus for high temperature (at least about 500-800.degree. C.) processing of semiconductor wafers. The systems, methods and apparatus of the present invention allow multiple process steps to be performed in situ in the same chamber to reduce total processing time and to ensure high quality processing for high aspect ratio devices. Performing multiple process steps in the same chamber also increases the control of the process parameters and reduces device damage. In particular, the present invention can provide high temperature deposition, heating and efficient cleaning for forming dielectric films having thickness uniformity, good gap fill capability, high density, low moisture, and other desired characteristics.

摘要翻译： 本发明提供用于半导体晶片的高温（至少约500-800℃）处理的系统，方法和装置。 本发明的系统，方法和装置允许多个工艺步骤在相同的腔室中原位进行，以减少总处理时间，并确保对高宽比装置的高质量处理。 在同一个室内执行多个工艺步骤也可以增加工艺参数的控制并减少设备损坏。 特别地，本发明可以提供用于形成具有厚度均匀性，良好间隙填充能力，高密度，低湿度和其它所需特性的介电膜的高温沉积，加热和有效清洁。

公开(公告)号：US08741775B2

公开(公告)日：2014-06-03

申请号：US13187224

申请日：2011-07-20

申请人： Srinivas D. Nemani ,  Yifeng Zhou ,  Dmitry Lubomirsky ,  Ellie Yieh

发明人： Srinivas D. Nemani ,  Yifeng Zhou ,  Dmitry Lubomirsky ,  Ellie Yieh

IPC分类号： H01L21/3105

CPC分类号： H01L21/3105 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144

摘要： Methods of patterning low-k dielectric films are described. For example, a method includes forming and patterning a mask layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. Exposed portions of the low-k dielectric layer are modified with a plasma process. The modified portions of the low-k dielectric layer are removed selective to the mask layer and unmodified portions of the low-k dielectric layer.

摘要翻译： 描述了低k介电膜图案的方法。 例如，一种方法包括在低k电介质层之上形成和图案化掩模层，低k电介质层设置在衬底之上。 低等离子体介质层的露出部分用等离子体工艺进行改性。 低k电介质层的修改部分被选择性地去除低k电介质层的掩模层和未修饰部分。

公开(公告)号：US20060141805A1

公开(公告)日：2006-06-29

申请号：US11358793

申请日：2006-02-21

申请人： Srinivas Nemani ,  Li-Qun Xia ,  Dian Sugiarto ,  Ellie Yieh ,  Ping Xu ,  Francimar Campana-Schmitt ,  Jia Lee

发明人： Srinivas Nemani ,  Li-Qun Xia ,  Dian Sugiarto ,  Ellie Yieh ,  Ping Xu ,  Francimar Campana-Schmitt ,  Jia Lee

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/76834 ,  C23C16/325 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/314 ,  H01L21/3148 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/7681 ,  H01L21/76826 ,  H01L21/76829 ,  Y10S438/931

摘要： A method of forming a silicon carbide layer for use in integrated circuit fabrication processes is provided. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a dopant in the presence of an electric field. The as-deposited silicon carbide layer has a compressibility that varies as a function of the amount of dopant present in the gas mixture during later formation.