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    METHOD AND PROCESS FOR REDUCING UNDERCOOLING IN A LEAD-FREE TIN-RICH SOLDER ALLOY
    2.
    发明申请
    METHOD AND PROCESS FOR REDUCING UNDERCOOLING IN A LEAD-FREE TIN-RICH SOLDER ALLOY 失效
    无铅无铅焊料合金的减少方法和工艺

    公开(公告)号：US20080290142A1

    公开(公告)日：2008-11-27

    申请号：US11752382

    申请日：2007-05-23

    申请人： Gareth G. Hougham ,  Kamalesh K. Srivastava ,  Sung K. Kang ,  Da-Yuan Shih ,  Brian R. Sundlof ,  S. Jay Chey ,  Donald W. Henderson ,  David R. Di Milia ,  Richard P. Ferlita ,  Roy A. Carruthers

    发明人： Gareth G. Hougham ,  Kamalesh K. Srivastava ,  Sung K. Kang ,  Da-Yuan Shih ,  Brian R. Sundlof ,  S. Jay Chey ,  Donald W. Henderson ,  David R. Di Milia ,  Richard P. Ferlita ,  Roy A. Carruthers

    IPC分类号： B23K35/24 ,  B23K101/36 ,  B23K31/02

    CPC分类号： B23K1/19 ,  B23K35/262 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/0215

    摘要： Briefly, a novel material process is disclosed wherein one or more nucleation modifiers are added, in trace amounts, to a lead-free tin-rich solder alloy to produce a solder composition with reduce or suppressed undercooling temperature characteristics. The modifier being a substance which facilitates the reduction of extreme anisotropic properties associated with body-centered-tetragonal tin based lead-free solder. The addition of the nucleation modifiers to the solder alloy does not materially effect the solder composition's melting point. As such, balls of solder with the nucleated composition freeze while other solder balls within the array remain in the melt. This effectively enables one substrate to be pinned to another substrate by one or more predetermined solder balls to secure the package while the remaining solder joints are in the liquid state. Further, the addition of a trace amount of nucleation sites within the composition facilitates control over the number, size, and orientations of primary intermetallic compounds in tin rich crystallite grains. Moreover, trace amounts of one or more solid and/or insoluble nucleating modifiers within a given volume of solder reduces the size of average crystallites within the composition.

    摘要翻译： 简而言之，公开了一种新颖的材料方法，其中将一种或多种成核改性剂以微量添加到无铅富锡焊料合金中以产生具有降低或抑制的过冷温度特性的焊料组合物。 该改性剂是有助于减少与体心四方锡锡基无铅焊料相关的极端各向异性的物质。 将成核改性剂添加到焊料合金中不会实质上影响焊料组合物的熔点。 因此，具有成核组合物的焊料球冻结，而阵列内的其它焊球保持在熔体中。 这有效地使一个基板通过一个或多个预定的焊球被固定到另一个基板，以固定封装，而剩余的焊点处于液态。 此外，在组合物中添加微量的成核位点有助于控制富锡微晶颗粒中初级金属间化合物的数量，尺寸和取向。 此外，在给定体积的焊料中痕量的一种或多种固态和/或不溶性成核改性剂减少了组合物内平均微晶的尺寸。

    Method and process for reducing undercooling in a lead-free tin-rich solder alloy
    3.
    发明授权
    Method and process for reducing undercooling in a lead-free tin-rich solder alloy 有权
    在无铅富锡焊料合金中减少过冷的方法和工艺

    公开(公告)号：US07784669B2

    公开(公告)日：2010-08-31

    申请号：US12536122

    申请日：2009-08-05

    申请人： Gareth G. Hougham ,  Kamalesh K. Srivastava ,  Sung K. Kang ,  Da-Yuan Shih ,  Brian R. Sundlof ,  S. Jay Chey ,  Donald W. Henderson ,  David R. Di Milia ,  Richard P. Ferlita ,  Roy A. Carruthers

    发明人： Gareth G. Hougham ,  Kamalesh K. Srivastava ,  Sung K. Kang ,  Da-Yuan Shih ,  Brian R. Sundlof ,  S. Jay Chey ,  Donald W. Henderson ,  David R. Di Milia ,  Richard P. Ferlita ,  Roy A. Carruthers

    IPC分类号： B23K35/24

    CPC分类号： B23K1/19 ,  B23K35/262 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/0215

    摘要： Briefly, a novel material process is disclosed wherein one or more nucleation modifiers are added, in trace amounts, to a lead-free tin-rich solder alloy to produce a solder composition with reduce or suppressed undercooling temperature characteristics. The modifier being a substance which facilitates the reduction of extreme anisotropic properties associated with body-centered-tetragonal tin based lead-free solder. The addition of the nucleation modifiers to the solder alloy does not materially effect the solder composition's melting point. As such, balls of solder with the nucleated composition freeze while other solder balls within the array remain in the melt. This effectively enables one substrate to be pinned to another substrate by one or more predetermined solder balls to secure the package while the remaining solder joints are in the liquid state. Further, the addition of a trace amount of nucleation sites within the composition facilitates control over the number, size, and orientations of primary intermetallic compounds in tin rich crystallite grains. Moreover, trace amounts of one or more solid and/or insoluble nucleating modifiers within a given volume of solder reduces the size of average crystallites within the composition.

    摘要翻译： 简而言之，公开了一种新颖的材料方法，其中将一种或多种成核改性剂以微量添加到无铅富锡焊料合金中以产生具有降低或抑制的过冷温度特性的焊料组合物。 该改性剂是有助于减少与体心四方锡锡基无铅焊料相关的极端各向异性的物质。 将成核改性剂添加到焊料合金中不会实质上影响焊料组合物的熔点。 因此，具有成核组合物的焊料球冻结，而阵列内的其它焊球保持在熔体中。 这有效地使一个基板通过一个或多个预定的焊球被固定到另一个基板，以固定封装，而剩余的焊点处于液态。 此外，在组合物中添加微量的成核位点有助于控制富锡微晶颗粒中初级金属间化合物的数量，尺寸和取向。 此外，在给定体积的焊料中痕量的一种或多种固态和/或不溶性成核改性剂减少了组合物内平均微晶的尺寸。

    TWO MASK PROCESS FOR ELECTROPLATING METAL EMPLOYING A NEGATIVE ELECTROPHORETIC PHOTORESIST
    6.
    发明申请
    TWO MASK PROCESS FOR ELECTROPLATING METAL EMPLOYING A NEGATIVE ELECTROPHORETIC PHOTORESIST 有权
    用于电镀金属的两个掩模工艺使用负极电泳光电

    公开(公告)号：US20140242524A1

    公开(公告)日：2014-08-28

    申请号：US13584326

    申请日：2012-08-13

    申请人： Gareth G. Hougham ,  Gerard McVicker ,  Anna Pratt

    发明人： Gareth G. Hougham ,  Gerard McVicker ,  Anna Pratt

    IPC分类号： G03F7/20 ,  G03F7/40

    CPC分类号： C25D17/12 ,  C25D1/003 ,  C25D5/022 ,  C25D13/00 ,  G03F7/0037 ,  G03F7/2022 ,  G03F7/203 ,  Y10T428/24562

    摘要： A negative electrophoretic photoresist is applied over a plurality of protruding disposable template portions on a substrate. A silo structure is placed on planar portions of the negative electrophoretic photoresist that laterally surround the plurality of protruding disposable template portions. The negative electrophoretic photoresist is lithographically exposed employing the silo structure and a first lithographic mask, which includes a transparent substrate with isolated opaque patterns thereupon. After removal of the silo structure, the negative electrophoretic photoresist is lithographically exposed employing a second lithographic mask, which includes a pattern of transparent areas overlying the planar portions of the negative electrophoretic photoresist less the areas for bases of metal structure to be subsequently formed by electroplating. The negative electrophoretic photoresist is developed to form cavities therein, and metal structures are formed by electroplating within the cavities. The negative electrophoretic photoresist and the plurality of protruding disposable template portions can be subsequently removed.

    摘要翻译： 将负电泳光致抗蚀剂施加在基板上的多个突出的一次性模板部分上。 筒状结构放置在横向包围多个突出的一次性模板部分的负电泳光致抗蚀剂的平面部分上。 负电泳光致抗蚀剂利用筒仓结构和第一平版印刷掩模进行光刻曝光，第一光刻掩模包括具有分离的不透明图案的透明基板。 在除去筒仓结构之后，使用第二光刻掩模将负电泳光致抗蚀剂光刻曝光，其包括覆盖负电泳光致抗蚀剂的平面部分的透明区域的图案，以减少随后通过电镀形成的金属结构基底的区域 。 负电泳光致抗蚀剂被开发以在其中形成空腔，并且通过在腔内电镀形成金属结构。 负电泳光致抗蚀剂和多个突出的一次性模板部分可以随后被去除。

    Through board stacking of multiple LGA-connected components
    7.
    发明授权
    Through board stacking of multiple LGA-connected components 有权
    通过板堆叠多个LGA连接的组件

    公开(公告)号：US08278745B2

    公开(公告)日：2012-10-02

    申请号：US12543104

    申请日：2009-08-18

    申请人： Paul W. Coteus ,  Shawn A. Hall ,  Gareth G. Hougham ,  Alphonso P. Lanzetta ,  Rick A. Rand

    发明人： Paul W. Coteus ,  Shawn A. Hall ,  Gareth G. Hougham ,  Alphonso P. Lanzetta ,  Rick A. Rand

    IPC分类号： H01L23/52

    CPC分类号： H05K3/325 ,  H05K2201/0314 ,  H05K2201/10545 ,  H05K2201/10719 ,  H05K2201/2018

    摘要： A package design is provided where a chip module is connected to a printed circuit board (PCB) via a land grid array (LGA) on the top surface of the PCB, and where a power supply is connected to the PCB via a second LGA on the bottom surface of the PCB. The stack of the chip module, power supply, and LGA is held in place and compressed with actuation hardware forming an adjustable frame. The package allows field replacibility of either the module, or the PS, and provides the shortest possible wiring distance from the PS to the module leading to higher performance.

    摘要翻译： 提供了一种封装设计，其中芯片模块通过PCB顶表面上的焊盘网格阵列（LGA）连接到印刷电路板（PCB），并且电源通过第二个LGA连接到PCB PCB的底面。 芯片模块，电源和LGA的堆叠被保持就位并用致动硬件压缩形成可调节的框架。 该封装允许模块或PS的现场可替代性，并提供从PS到模块的最短可能布线距离，从而实现更高的性能。