公开(公告)号：US20070163109A1

公开(公告)日：2007-07-19

申请号：US11321426

申请日：2005-12-29

申请人： Hem Takiar ,  Manickam Thavarajah ,  Ken Wang ,  Chih-Chin Liao ,  Andre McKenzie ,  Shrikar Bhagath ,  Han-Shiao Chen ,  Chin-Tien Chiu

发明人： Hem Takiar ,  Manickam Thavarajah ,  Ken Wang ,  Chih-Chin Liao ,  Andre McKenzie ,  Shrikar Bhagath ,  Han-Shiao Chen ,  Chin-Tien Chiu

IPC分类号： H01R43/00

CPC分类号： H01L23/544 ,  H01L21/4857 ,  H01L21/50 ,  H01L21/561 ,  H01L23/49565 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54486 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83801 ,  H01L2224/83851 ,  H01L2224/85 ,  H01L2224/97 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/30107 ,  Y10T29/49117 ,  H01L2924/00012 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A strip on which a plurality of integrated circuit package outlines may be fabricated within a plurality of process tools. The strip includes one or more fiducial notches and/or guide pin notches formed in an outer edge of the strip. The one or more fiducial and/or guide pin notches allow a position of the strip to be identified within at least one process tool of the plurality of process tools. By forming the notches in the outer periphery of the strip, the usable area on the strip on which integrated circuit package outlines may be formed is increased. The strip may alternatively include conventional fiducial and/or guide pin holes, with the molding compound applied at least partially around the holes on one or more sides of the strip. The strip may further alternatively include fiducial holes filled with a translucent material that provides stability to the strip while allowing the strip to be used with an optical recognition sensor.

摘要翻译： 其上可以在多个处理工具内制造多个集成电路封装轮廓的条带。 带材包括形成在带的外边缘中的一个或多个基准凹口和/或导向销切口。 一个或多个基准和/或引导销凹口允许在多个处理工具的至少一个处理工具内识别条带的位置。 通过在带的外周形成切口，可以形成集成电路封装轮廓的带上的可用区域。 条带可替代地包括常规的基准和/或引导销孔，模制化合物至少部分地围绕带的一侧或多侧上的孔施加。 条带还可以包括填充有半透明材料的基准孔，其为条带提供稳定性，同时允许条带与光学识别传感器一起使用。

公开(公告)号：US20070108257A1

公开(公告)日：2007-05-17

申请号：US11280419

申请日：2005-11-16

申请人： Chih-Chin Liao ,  Ken Wang ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Jack Chien ,  Shrikar Bhagath ,  Cheemen Yu ,  Hem Takiar

发明人： Chih-Chin Liao ,  Ken Wang ,  Han-Shiao Chen ,  Chin-Tien Chiu ,  Jack Chien ,  Shrikar Bhagath ,  Cheemen Yu ,  Hem Takiar

IPC分类号： B23K31/02 ,  B23K31/00

CPC分类号： H05K1/111 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K3/3421 ,  H05K3/3442 ,  H05K3/3452 ,  H05K2201/09427 ,  H05K2201/09663 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10636 ,  H05K2201/10689 ,  H05K2201/10727 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00014

摘要： A semiconductor package having a low profile is disclosed. In embodiments, a surface mounted component may be mounted directly to the core of the semiconductor package substrate, so that there is no conductive layer, plating layers or solder paste between the component and the substrate core. The surface mounted component may be any type of component which may be surface mounted on a substrate according to an SMT process, including for example passive components and various packaged semiconductors.

摘要翻译： 公开了一种具有低轮廓的半导体封装。 在实施例中，表面安装部件可以直接安装到半导体封装基板的芯部，使得在部件和基板芯之间不存在导电层，镀层或焊膏。 表面安装部件可以是根据SMT工艺可以表面安装在基板上的任何类型的部件，包括例如无源部件和各种封装半导体。

公开(公告)号：US20080054445A1

公开(公告)日：2008-03-06

申请号：US11930816

申请日：2007-10-31

申请人： Chin-Tien Chiu ,  Chih-Chin Liao ,  Ken Wang ,  Han-Shiao Chen ,  Cheemen Yu ,  Hem Takiar

发明人： Chin-Tien Chiu ,  Chih-Chin Liao ,  Ken Wang ,  Han-Shiao Chen ,  Cheemen Yu ,  Hem Takiar

IPC分类号： H01L23/12 ,  H01L21/00

CPC分类号： H01L23/562 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/48 ,  H01L23/49805 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/528 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05015 ,  H01L2224/05023 ,  H01L2224/0605 ,  H01L2224/06151 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1438 ,  H01L2924/15313 ,  H01L2924/15323 ,  H01L2924/15333 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking.

摘要翻译： 形成在半导体管芯封装中的衬底的第一侧上的刚性波形图案。 刚性波形图案与形成在基板的第二侧上的接触指状物对准并覆盖在其上。 当模制过程中衬底和裸片被封装时，刚性波形有效地减少了模具的变形和应力，从而大大减轻了模具开裂。

公开(公告)号：US20070152319A1

公开(公告)日：2007-07-05

申请号：US11321929

申请日：2005-12-29

申请人： Hem Takiar ,  Cheemen Yu ,  Ken Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

发明人： Hem Takiar ,  Cheemen Yu ,  Ken Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

IPC分类号： H01L23/48

CPC分类号： H01L25/0657 ,  H01L21/3205 ,  H01L23/04 ,  H01L23/3121 ,  H01L23/5386 ,  H01L24/48 ,  H01L24/64 ,  H01L24/65 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.

摘要翻译： 公开了一种加强的半导体管芯基板和封装。 衬底可以包括形成有非线性边缘的接触指状物。 向接触指边缘提供非线性轮廓减少了施加在半导体管芯上的机械应力，否则这些应力将以直接接触指的边缘发生。 衬底可以附加地或可选地包括从接触指一定角度延伸的电镀迹线。 以一定角度延伸，至少衬底边缘处的电镀迹线的端部被覆盖在半导体封装被封装的盖子的下方。 因此，当与主机设备一起使用时，避免了盖子下方的电镀痕迹的端部和主机设备的接触销之间的接触。

公开(公告)号：US20060231943A1

公开(公告)日：2006-10-19

申请号：US11106699

申请日：2005-04-14

申请人： Chin-Tien Chiu ,  Chih-Chin Liao ,  Ken Wang ,  Han-Shiao Chen ,  Cheemen Yu ,  Hem Takiar

发明人： Chin-Tien Chiu ,  Chih-Chin Liao ,  Ken Wang ,  Han-Shiao Chen ,  Cheemen Yu ,  Hem Takiar

IPC分类号： H01L23/12

CPC分类号： H01L23/562 ,  H01L21/56 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/48 ,  H01L23/49805 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/528 ,  H01L24/05 ,  H01L24/06 ,  H01L24/32 ,  H01L24/33 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05015 ,  H01L2224/05023 ,  H01L2224/0605 ,  H01L2224/06151 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/0102 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1438 ,  H01L2924/15313 ,  H01L2924/15323 ,  H01L2924/15333 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A rigid wave pattern formed on a first side of a substrate in a semiconductor die package. The rigid wave pattern aligns with and overlies the contact fingers formed on the second side of the substrate. When the substrate and dice are encased during the molding process, the rigid wave pattern effectively reduces deformation of and stresses on the dice, therefore substantially alleviating die cracking.

摘要翻译： 形成在半导体管芯封装中的衬底的第一侧上的刚性波形图案。 刚性波形图案与形成在基板的第二侧上的接触指状物对准并覆盖在其上。 当模制过程中衬底和裸片被封装时，刚性波形有效地减少了模具的变形和应力，从而大大减轻了模具开裂。

公开(公告)号：US20070155247A1

公开(公告)日：2007-07-05

申请号：US11321931

申请日：2005-12-29

申请人： Hem Takiar ,  Cheemen Yu ,  Ken Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

发明人： Hem Takiar ,  Cheemen Yu ,  Ken Wang ,  Chin-Tien Chiu ,  Han-Shiao Chen ,  Chih-Chin Liao

IPC分类号： H01R24/00

CPC分类号： H01L23/49838 ,  H01L23/3121 ,  H01L23/49811 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/30107 ,  H05K1/117 ,  H05K3/242 ,  H05K3/3452 ,  H05K2201/09281 ,  H05K2201/09381 ,  H05K2201/0939 ,  H05K2201/099 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.

摘要翻译： 公开了一种加强的半导体管芯基板和封装。 衬底可以包括形成有非线性边缘的接触指状物。 向接触指边缘提供非线性轮廓减少了施加在半导体管芯上的机械应力，否则这些应力将以直接接触指的边缘发生。 衬底可以附加地或可选地包括从接触指一定角度延伸的电镀迹线。 以一定角度延伸，至少衬底边缘处的电镀迹线的端部被覆盖在半导体封装被封装的盖子的下方。 因此，当与主机设备一起使用时，避免了盖子下方的电镀痕迹的端部和主机设备的接触销之间的接触。

公开(公告)号：US20070132066A1

公开(公告)日：2007-06-14

申请号：US11301715

申请日：2005-12-13

申请人： Hem Takiar ,  Ken Wang ,  Chih-Chin Liao ,  Han-Shiao Chen

发明人： Hem Takiar ,  Ken Wang ,  Chih-Chin Liao ,  Han-Shiao Chen

IPC分类号： H01L23/544

CPC分类号： H05K3/242 ,  H01L21/4846 ,  H01L23/49838 ,  H01L24/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H05K3/0052 ,  H05K2201/09263 ,  H01L2924/00

摘要： A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.

摘要翻译： 公开了半导体管芯衬底面板，其包括在面板上相邻的半导体封装轮廓之间的最小间隙宽度，同时确保电镀电端子的电隔离。 通过减小相邻封装轮廓之间的边界的宽度，在半导体封装的衬底面板上获得额外的空间。

公开(公告)号：US20070004094A1

公开(公告)日：2007-01-04

申请号：US11171095

申请日：2005-06-30

申请人： Hem Takiar ,  Shrikar Bhagath ,  Ken Wang

发明人： Hem Takiar ,  Shrikar Bhagath ,  Ken Wang

IPC分类号： H01L21/58

CPC分类号： H01L23/49855 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0224 ,  H05K1/0253 ,  H05K1/0271 ,  H05K2201/09681 ,  H05K2201/09781 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A dummy circuit pattern is disclosed on a surface of a substrate for a semiconductor package, the dummy circuit pattern including straight line segments having a length controlled so as not to generate stresses within the line segments above a desired stress. The dummy circuit pattern may be formed of lines, or contiguous or spaced polygons, such as hexagons. Portions of the dummy circuit pattern may also be formed with an orientation, size and position that are randomly selected.

摘要翻译： 公开了用于半导体封装的衬底的表面上的虚拟电路图案，该虚拟电路图案包括直线段，其长度受到控制，以便不在所述线段内产生高于所需应力的应力。 虚拟电路图案可以由线或邻接的或间隔开的多边形（例如六边形）形成。 虚拟电路图案的部分也可以形成为随机选择的取向，尺寸和位置。

公开(公告)号：US20070001285A1

公开(公告)日：2007-01-04

申请号：US11170883

申请日：2005-06-30

申请人： Hem Takiar ,  Shrikar Bhagath ,  Ken Wang

发明人： Hem Takiar ,  Shrikar Bhagath ,  Ken Wang

IPC分类号： H01L23/12

CPC分类号： H01L23/3121 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06527 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H05K1/0224 ,  H05K1/0253 ,  H05K1/0271 ,  H05K2201/09681 ,  H05K2201/0969 ,  H05K2201/09781 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A dummy circuit pattern is disclosed on a surface of a substrate for a semiconductor package, the dummy circuit pattern including straight line segments having a length controlled so as not to generate stresses within the line segments above a desired stress. The dummy circuit pattern may be formed of lines, or contiguous or spaced polygons, such as hexagons. Portions of the dummy circuit pattern may also be formed with an orientation, size and position that are randomly selected.

摘要翻译： 公开了用于半导体封装的衬底的表面上的虚拟电路图案，该虚拟电路图形包括直线段，该直线段的长度受到控制，以便不在所述线段内产生高于所需应力的应力。 虚拟电路图案可以由线或邻接的或间隔开的多边形（例如六边形）形成。 虚拟电路图案的部分也可以形成为随机选择的取向，尺寸和位置。

公开(公告)号：US20070218588A1

公开(公告)日：2007-09-20

申请号：US11750768

申请日：2007-05-18

申请人： Hem Takiar ,  Shrikar Bhagath ,  Ken Wang

发明人： Hem Takiar ,  Shrikar Bhagath ,  Ken Wang

IPC分类号： H01L21/00

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48147 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06562 ,  H01L2924/01004 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： Improved techniques for stacking integrated circuit dies within an integrated circuit package are disclosed. These improved techniques allow greater stacking density of integrated circuit dies within an integrated circuit package. Additionally, the improved stacking techniques permit conventional bonding techniques for electrical connection of the various integrated circuit dies to each other or to a substrate. These improved approaches are particularly useful for stacking same size (and often same function) integrated circuit dies within integrated circuit packages. One example of such an integrated circuit package is a non-volatile memory integrated circuit package that contains multiple, like-sized memory storage integrated circuit dies arranged in a stack.

摘要翻译： 公开了用于在集成电路封装内堆叠集成电路管芯的改进的技术。 这些改进的技术允许集成电路封装内的集成电路管芯的堆叠密度更高。 此外，改进的堆叠技术允许用于将各种集成电路管芯彼此或与衬底电连接的常规焊接技术。 这些改进的方法对于在集成电路封装内堆叠相同尺寸（并且通常是相同功能的）集成电路管芯特别有用。 这种集成电路封装的一个例子是非易失性存储器集成电路封装，其包含堆叠地布置的多个相同大小的存储器集成电路管芯。