利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

16 条记录 (耗时 0.032 秒)

    Macroporous support for chemical amplification reactions
    3.
    发明申请
    Macroporous support for chemical amplification reactions 审中-公开
    大孔支持化学扩增反应

    公开(公告)号：US20060263799A1

    公开(公告)日：2006-11-23

    申请号：US11357731

    申请日：2006-02-17

    申请人： Stephan Dertinger ,  Marco Kluehr ,  Thomas Haneder

    发明人： Stephan Dertinger ,  Marco Kluehr ,  Thomas Haneder

    IPC分类号： C12Q1/68 ,  C12P19/34 ,  C12M1/34

    CPC分类号： B01L3/50857 ,  B01L2200/16 ,  B01L2300/069 ,  B01L2300/0819 ,  B01L2300/0893 ,  C12Q1/686 ,  C12Q2523/308

    摘要： A method for carrying out an amplification of nucleic acids in pores of a two-dimensionally designed macroporous support material according to one embodiment includes the step of providing a predetermined part of a reaction mixture necessary for the amplification of a nucleic acid in pores of the support material. A device for carrying out the amplification of nucleic acids according to one embodiment includes a two-dimensionally designed macroporous support material having a multiplicity of pores, wherein a predetermined part of a reaction mixture for carrying out an amplification of nucleic acids is provided in the pores.

    摘要翻译： 根据一个实施方案的用于在二维设计的大孔载体材料的孔中进行核酸扩增的方法包括以下步骤：提供必​​要的预定部分的反应混合物，所述反应混合物在载体的孔中扩增核酸 材料。 根据一个实施方案的用于进行核酸扩增的装置包括具有多个孔的二维设计的大孔载体材料，其中在孔中提供用于进行核酸扩增的反应混合物的预定部分 。

    Chip carrier with reduced interference signal sensitivity
    4.
    发明授权
    Chip carrier with reduced interference signal sensitivity 有权
    具有降低干扰信号灵敏度的芯片载体

    公开(公告)号：US07911026B2

    公开(公告)日：2011-03-22

    申请号：US11618172

    申请日：2006-12-29

    申请人： Florian Binder ,  Thomas Haneder ,  Judith Lehmann ,  Manfred Schneegans ,  Grit Sommer

    发明人： Florian Binder ,  Thomas Haneder ,  Judith Lehmann ,  Manfred Schneegans ,  Grit Sommer

    IPC分类号： H01L21/02

    CPC分类号： H01L23/49827 ,  H01L23/50 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2224/05026 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/0102 ,  H01L2924/09701 ,  H01L2924/15311 ,  H05K1/162 ,  H05K3/4602 ,  H01L2224/05599

    摘要： Carrier including: a substrate having a first interface with first contact holes, and a second interface, which lies opposite the first interface, with second contact holes. The substrate includes a substrate body and electrically conductive contact channels formed therein, wherein each of the contact channels electrically conductively connects a first contact hole to a second contact hole. The carrier also includes a front-side wiring layer arranged on the first interface and; has a first front-side metallization layer formed therein such that it includes a first capacitor electrode for electrically connecting microelectronic devices and/or circuits to a first pole of a signal or supply voltage. The first capacitor electrode, at least partly via a capacitor dielectric formed in the carrier, couples capacitively to electrically conductive regions of a second front-side metallization layer and/or the substrate which at least partly form a second capacitor electrode for electrically connecting the microelectronic devices and/or circuits to a second pole of the signal or supply voltage.

    摘要翻译： 载体包括：具有与第一接触孔的第一界面的基底和与第一界面相对的第二界面与第二接触孔。 基板包括基板主体和形成在其中的导电接触通道，其中每个接触通道将第一接触孔电连接到第二接触孔。 载体还包括布置在第一界面上的前侧布线层， 具有形成在其中的第一前侧金属化层，使得其包括用于将微电子器件和/或电路电连接到信号或电源电压的第一极的第一电容器电极。 至少部分地经由形成在载体中的电容器电介质的第一电容器电极电容耦合到第二前侧金属化层和/或衬底的导电区域，该区域至少部分地形成第二电容器电极，用于电连接微电子 设备和/或电路连接到信号或电源电压的第二极点。

    FEMFET device and method for producing same
    6.
    发明授权
    FEMFET device and method for producing same 失效
    FEMFET器件及其制造方法

    公开(公告)号：US06737689B1

    公开(公告)日：2004-05-18

    申请号：US09857262

    申请日：2001-07-16

    申请人： Till Schlösser ,  Thomas Haneder

    发明人： Till Schlösser ,  Thomas Haneder

    IPC分类号： H01L2976

    CPC分类号： H01L21/28291 ,  H01L28/56 ,  H01L29/516

    摘要： The present invention relates to a FEMFET device with a semiconductor substrate and to at least one field effect transistor that is provided in the semiconductor substrate. The field effect transistor has a source area, a drain area, a channel area and a gate stack. The gate stack has at least one ferroelectric layer and at least one thin diffusion barrier layer being arranged between the lowest ferroelectric layer and the semiconductor substrate and being configured in such a way that an out-diffusion of the components of the ferroelectric layer into the semiconductor substrate is essentially prevented.

    摘要翻译： 本发明涉及具有半导体衬底和设置在半导体衬底中的至少一个场效应晶体管的FEMFET器件。 场效应晶体管具有源极区域，漏极区域，沟道区域和栅极堆叠。 栅极堆叠具有至少一个铁电层，并且至少一个薄扩散阻挡层被布置在最低铁电层和半导体衬底之间，并且被配置为使得铁电层的组分向半导体内扩散 基本上被防止。

    Ferroelectric transistor and method for fabricating it
    7.
    发明授权
    Ferroelectric transistor and method for fabricating it 有权
    铁电晶体管及其制造方法

    公开(公告)号：US06538273B2

    公开(公告)日：2003-03-25

    申请号：US09849910

    申请日：2001-05-04

    申请人： Josef Willer ,  Georg Braun ,  Till Schlösser ,  Thomas Haneder

    发明人： Josef Willer ,  Georg Braun ,  Till Schlösser ,  Thomas Haneder

    IPC分类号： H01L2902

    CPC分类号： H01L29/78391

    摘要： A ferroelectric transistor is disclosed which has two source/drain regions and a channel region disposed in between in a semiconductor substrate. A metallic intermediate layer is disposed on the surface of the channel region and forms a Schottky diode with the semiconductor substrate, and a ferroelectric layer and a gate electrode are disposed on its surface. The ferroelectric transistor is fabricated using steps appertaining to silicon process technology.

    摘要翻译： 公开了具有两个源极/漏极区域和设置在半导体衬底之间的沟道区域的铁电晶体管。 金属中间层设置在沟道区域的表面上，并与半导体衬底形成肖特基二极管，并且在其表面上设置铁电层和栅电极。 铁电晶体管使用与硅工艺技术相关的步骤制造。

    Chip carrier substrate and production method therefor
    8.
    发明申请
    Chip carrier substrate and production method therefor 审中-公开
    芯片载体基板及其制造方法

    公开(公告)号：US20080308303A1

    公开(公告)日：2008-12-18

    申请号：US11486671

    申请日：2006-07-14

    申请人： Volker Lehmann ,  Florian Binder ,  Thomas Haneder ,  Alfred Martin ,  Judith Lehmann

    发明人： Volker Lehmann ,  Florian Binder ,  Thomas Haneder ,  Alfred Martin ,  Judith Lehmann

    IPC分类号： H05K1/03 ,  H05K3/10

    CPC分类号： H01L21/486 ,  H01L23/147 ,  H01L23/481 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/05599

    摘要： Method for producing a macroporous silicon substrate suitable as a carrier for microelectronic components. Blind holes are produced from a front surface of the substrate. An insulator layer is produced on the front and rear surfaces of the substrate. Selective isotropic etching is performed from the rear surface with uncovering of blind hole ends produced such that respective blind hole walls formed by the insulator layer project from the substrate on the rear surface and are defined in this region only by the insulator layer forming the respective blind hole wall. A further insulator layer is then produced on the surfaces of the substrate. A plurality of the blind holes are then filled with a metal or a metal alloy by introducing the substrate into a melt thereof under pressure in a process chamber containing the melt. The melt is then asymmetrically cooled in the blind holes from the front surface, so that the metal or the alloy contracts toward and lies on a plane with the rear surface of the substrate. Any of the remaining unfilled blind hole ends that project from the substrate are removed.

    摘要翻译： 适用于微电子元件载体的大孔硅衬底的制造方法。 从基板的前表面产生盲孔。 在基板的前表面和后表面上产生绝缘体层。 从后表面进行选择性各向同性蚀刻，盲孔的露出被制成，使得由绝缘体层形成的各个盲孔壁从后表面上的基板突出，并且仅在形成该盲区的绝缘体层的该区域中限定 孔壁。 然后在衬底的表面上产生另外的绝缘体层。 然后通过在包含熔体的处理室中将基材在压力下引入其熔体中，用金属或金属合金填充多个盲孔。 然后熔融物在盲孔中从前表面不对称地冷却，使得金属或合金收缩并且位于与基底的后表面的平面上。 从衬底突出的任何剩余的未填充的盲孔端部被移除。