公开(公告)号：US09263784B2

公开(公告)日：2016-02-16

申请号：US14702194

申请日：2015-05-01

Applicant: IBIDEN CO., LTD.

Inventor： Yasushi Inagaki ,  Yasuhiro Takahashi ,  Satoshi Kurokawa

IPC: H05K1/00 ,  H01P3/08 ,  H05K1/11 ,  H05K1/18 ,  H05K1/02

CPC classification number: H01P3/081 ,  H05K1/0213 ,  H05K1/0228 ,  H05K1/0243 ,  H05K1/0251 ,  H05K1/111 ,  H05K1/181 ,  H05K3/3436 ,  H05K3/429 ,  H05K2201/10159

Abstract: A package substrate includes a core substrate, a first buildup layer and a second buildup layer. The first buildup layer includes an uppermost interlayer, an upper inner interlayer, an uppermost conductive layer including first pads and second pads, an upper first conductive layer, an upper second conductive layer, vias formed through the uppermost interlayer and connecting the upper first conductive layer and the second pads, and skip vias formed through the uppermost and upper inner interlayers and connecting the uppermost and upper second conductive layers. The second buildup layer includes a lowermost interlayer, a lower inner interlayer, a lowermost conductive layer including third pads, a lower first conductive layer, a lower second conductive layer, vias formed through the lowermost interlayer and connecting the lower first conductive layer and third pads, and skip vias formed through the lowermost and lower inner interlayers and connecting the lowermost and lower second conductive layers.

Abstract translation: 封装基板包括芯基板，第一堆积层和第二堆积层。 第一累积层包括最上层中间层，上内层中间层，包括第一焊盘和第二焊盘的最上层导电层，上第一导电层，上第二导电层，通过最上层中间层形成的通孔，并将上第一导电层 和第二焊盘，并且跳过通过最上层和上部内中间层形成的通孔，并连接最上面和上部第二导电层。 第二堆积层包括最下层的中间层，下层的内层，包含第三层的最下层的导电层，下部的第一导电层，下部的第二导电层，通过最下层的中间层形成的通孔，并连接下部第一导电层和第三层 并且跳过通过最下部和下部内部中间层形成的通孔并连接最下部和下部第二导电层。

公开(公告)号：US09326377B2

公开(公告)日：2016-04-26

申请号：US13953150

申请日：2013-07-29

Applicant: IBIDEN Co., Ltd.

Inventor： Haruhiko Morita ,  Shinobu Kato ,  Yasuhiko Mano ,  Satoshi Kurokawa

IPC: H05K1/00 ,  H05K1/03 ,  H05K1/16 ,  H05K1/11 ,  H05K3/46 ,  H05K1/02

CPC classification number: H05K1/0306 ,  H05K1/0219 ,  H05K1/024 ,  H05K3/4673 ,  H05K2201/0191

Abstract: A printed wiring board includes a first buildup layer including first and second interlayer insulating layers, and a second buildup layer formed on the first buildup layer and including the outermost interlayer insulating layer and the outermost conductive layer formed on the outermost interlayer resin insulating layer. The buildup layer includes a first signal line interposed between the first and second interlayer insulating layers, a first ground layer formed on a surface of the first interlayer resin insulating layer, and a second ground layer formed on a surface of the second interlayer resin insulating layer such that the first signal line is interposed between the first and second ground layers, the first and second interlayer insulating layers and the outermost interlayer insulating layer include resin materials, respectively, and the first and second interlayer insulating layers are different from the outermost interlayer insulating layer in material and/or thickness.

Abstract translation: 印刷电路板包括：第一累积层，包括第一和第二层间绝缘层;以及第二累积层，形成在第一堆积层上，并且包括最外层间绝缘层和形成在最外层间树脂绝缘层上的最外层导电层。 积层层包括插入在第一和第二层间绝缘层之间的第一信号线，形成在第一层间树脂绝缘层的表面上的第一接地层和形成在第二层间树脂绝缘层的表面上的第二接地层 使得第一信号线插入在第一和第二接地层之间，第一和第二层间绝缘层和最外层间绝缘层分别包括树脂材料，并且第一和第二层间绝缘层不同于最外层间绝缘层 材料层和/或厚度层。

公开(公告)号：US20150357316A1

公开(公告)日：2015-12-10

申请号：US14734065

申请日：2015-06-09

Applicant: IBIDEN CO., LTD.

Inventor： Yasushi INAGAKI ,  Yasuhiro Takahashi ,  Satoshi Kurokawa

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L23/528

CPC classification number: H01L25/18 ,  H01L21/4846 ,  H01L23/145 ,  H01L23/3157 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/528 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81395 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K3/4644 ,  H05K2201/0191 ,  H05K2201/0195 ,  H05K2201/09918 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A package substrate includes an inner interlayer, a first conductor layer on the inner interlayer, a second conductor layer on which the inner interlayer is formed, an outermost interlayer on the first conductor layer, an outermost conductor layer on the outermost interlayer and including first and second pads positioned to mount first and second electronic components on the outermost interlayer, outermost vias connecting the first and outermost conductor layers through the outermost interlayer, and skip vias connecting the outermost and second conductor layers through the outermost and inner interlayers. The first conductor layer includes a first circuit connecting two outermost vias, and the outermost conductor layer includes an outermost circuit connecting one of the two outermost vias and one skip via such that the first conductor circuit, two outermost vias, outermost circuit and one skip via form a connection path connecting one second pad and the second conductor layer.

Abstract translation: 封装基板包括内夹层，内层中的第一导体层，形成有内层的第二导体层，第一导体层上的最外层，最外层的最外层导体层， 定位成将第一和第二电子部件安装在最外层中间的第二焊盘，通过最外层间连接第一和最外层导体层的最外面通孔，以及通过最外层和内层间连接最外层和第二导体层的通孔。 第一导体层包括连接两个最外面通孔的第一电路，最外面的导体层包括连接两个最外面通孔中的一个的最外部电路和一个跳过通孔，使得第一导体电路，两个最外面的通孔，最外面的电路和一个跳过通孔 形成连接一个第二焊盘和第二导体层的连接路径。

公开(公告)号：US20150327363A1

公开(公告)日：2015-11-12

申请号：US14706269

申请日：2015-05-07

Applicant: IBIDEN CO., LTD.

Inventor： Yasushi INAGAKI ,  Yasuhiro Takahashi ,  Satoshi Kurokawa

IPC: H05K1/02 ,  H05K3/46 ,  H05K1/18 ,  H05K1/03 ,  H05K1/11

CPC classification number: H05K1/0243 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L25/18 ,  H01L2924/0002 ,  H05K1/0298 ,  H05K1/0313 ,  H05K1/112 ,  H05K1/115 ,  H05K1/181 ,  H05K3/4602 ,  H05K3/4611 ,  H05K3/4644 ,  H05K2201/0949 ,  H05K2201/09518 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A package substrate includes an inner interlayer, a first conductor layer, a second conductor layer, an outermost interlayer, an outermost conductor layer including first and second pads to mount electronic components, vias including first and second vias such that the first vias are connecting the first conductor layer and first pads and the second vias are connecting the first conductor layer and second pads, and skip vias penetrating through the outermost and inner interlayers such that the skip vias are connecting the outermost and second conductor layers. Sum of insulation distances (t1, t2) is in range of 40 μm or less to 10 μm or more, where the insulation distance (t1) is insulation distance between the outermost and first conductor layers and the insulation distance (t2) is insulation distance between the first and second conductor layers, and difference between the insulation distances (t1, t2) is less than 5 μm.

Abstract translation: 封装基板包括内层，第一导体层，第二导体层，最外层间，最外层导体层，包括用于安装电子元件的第一和第二焊盘，通孔包括第一和第二通孔，使得第一通孔连接 第一导体层和第一焊盘和第二通孔连接第一导体层和第二焊盘，并且跳过穿过最外层和内层的通孔，使得跳过通孔连接最外层导体层和第二导体层。 绝缘距离（t1，t2）之和在绝缘距离（t1）为最外层与第一导体层之间的绝缘距离与绝缘距离（t2）的绝缘距离（t2）为40μm以下至10μm以上的范围内， 在第一和第二导体层之间，绝缘距离（t1，t2）之间的差小于5μm。

公开(公告)号：US20140374150A1

公开(公告)日：2014-12-25

申请号：US14310354

申请日：2014-06-20

Applicant: IBIDEN CO., LTD.

Inventor： Yasushi INAGAKI ,  Yasuhiro Takahashi ,  Satoshi Kurokawa

IPC: H05K1/11 ,  H05K3/40

CPC classification number: H05K1/113 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K1/0298 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/09227 ,  H05K2201/09518 ,  H01L2924/00

Abstract: A package substrate includes an outermost interlayer resin insulation layer, an outermost conductive layer formed on a first surface of the outermost interlayer resin insulation layer and including first pads positioned to mount a first electronic component and second pads positioned to mount a second electronic component, a first conductive layer including first conductive circuits and formed on a second surface of the outermost interlayer resin insulation layer on the opposite side with respect to the first surface, first via conductors penetrating through the outermost interlayer resin insulation layer such that the first via conductors are connecting the first conductive layer and the first pads, and second via conductors penetrating through the outermost interlayer resin insulation layer such that the second via conductors are connecting the first conductive layer and the second pads. The first conductive circuits in the first conductive layer are connecting the first and second pads, respectively.

Abstract translation: 封装衬底包括最外层间树脂绝缘层，最外层导电层，其形成在最外层间树脂绝缘层的第一表面上，并且包括定位成安装第一电子部件的第一焊盘和定位成安装第二电子部件的第二焊盘; 第一导电层包括第一导电电路，并且相对于第一表面在相对侧的最外层间树脂绝缘层的第二表面上形成，第一通孔导体穿过最外层间树脂绝缘层，使得第一通孔导体连接 所述第一导电层和所述第一焊盘，以及穿过所述最外层间树脂绝缘层的第二通孔导体，使得所述第二通孔导体连接所述第一导电层和所述第二焊盘。 第一导电层中的第一导电电路分别连接第一和第二焊盘。

公开(公告)号：US09763319B2

公开(公告)日：2017-09-12

申请号：US14706269

申请日：2015-05-07

Applicant: IBIDEN CO., LTD.

Inventor： Yasushi Inagaki ,  Yasuhiro Takahashi ,  Satoshi Kurokawa

IPC: H05K7/00 ,  H05K1/02 ,  H05K1/03 ,  H05K1/11 ,  H05K1/18 ,  H05K3/46 ,  H01L23/538 ,  H01L25/18 ,  H01L23/498

CPC classification number: H05K1/0243 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5384 ,  H01L25/18 ,  H01L2924/0002 ,  H05K1/0298 ,  H05K1/0313 ,  H05K1/112 ,  H05K1/115 ,  H05K1/181 ,  H05K3/4602 ,  H05K3/4611 ,  H05K3/4644 ,  H05K2201/0949 ,  H05K2201/09518 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A package substrate includes an inner interlayer, a first conductor layer, a second conductor layer, an outermost interlayer, an outermost conductor layer including first and second pads to mount electronic components, vias including first and second vias such that the first vias are connecting the first conductor layer and first pads and the second vias are connecting the first conductor layer and second pads, and skip vias penetrating through the outermost and inner interlayers such that the skip vias are connecting the outermost and second conductor layers. Sum of insulation distances (t1, t2) is in range of 40 μm or less to 10 μm or more, where the insulation distance (t1) is insulation distance between the outermost and first conductor layers and the insulation distance (t2) is insulation distance between the first and second conductor layers, and difference between the insulation distances (t1, t2) is less than 5 μm.

公开(公告)号：US09443800B2

公开(公告)日：2016-09-13

申请号：US14669393

申请日：2015-03-26

Applicant: IBIDEN CO., LTD.

Inventor： Yasushi Inagaki ,  Yasuhiro Takahashi ,  Satoshi Kurokawa

IPC: H01L23/495 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/00 ,  H01L24/16 ,  H01L25/065 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/014

Abstract: A package substrate includes interlayer insulating layers including outermost and inner-layer layers, conductor layers including an outermost layer, a first layer between the outermost and inner-layer layers, and a second layer on which the inner-layer layer is formed, via conductors including first and second conductors through the outermost insulating layer, and skip via conductors through the outermost and inner-layer insulating layers to connect the outermost and second conductor layers. The outermost conductor layer includes first and second pads to mount first and second electronic components on the outermost insulating layer, the first conductors are positioned to connect the first conductor layer and first pads, the second conductors are positioned to connect the first conductor layer and second pads, and the first conductor layer has area on surface of the inner-layer insulating layer which is in range of 3 to 15% of area of the surface of the inner-layer insulating layer.

Abstract translation: 封装衬底包括包括最外层和内层层的层间绝缘层，包括最外层的导体层，最外层和内层层之间的第一层以及形成内层层的第二层，经由导体 包括穿过最外绝缘层的第一和第二导体，并且经由导体穿过最外层和内层绝缘层，以连接最外层和第二导体层。 最外面的导体层包括用于将第一和第二电子部件安装在最外绝缘层上的第一和第二焊盘，第一导体被定位成连接第一导体层和第一焊盘，第二导体定位成连接第一导体层和第二导体层 衬垫，并且第一导体层在内层绝缘层的表面上具有在内层绝缘层的表面的面积的3至15％范围内的面积。

公开(公告)号：US09287250B2

公开(公告)日：2016-03-15

申请号：US14734065

申请日：2015-06-09

Applicant: IBIDEN CO., LTD.

Inventor： Yasushi Inagaki ,  Yasuhiro Takahashi ,  Satoshi Kurokawa

IPC: H01L25/18 ,  H01L23/498 ,  H01L23/528 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/18 ,  H01L21/4846 ,  H01L23/145 ,  H01L23/3157 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/528 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0655 ,  H01L2224/11334 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2224/81395 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K3/4644 ,  H05K2201/0191 ,  H05K2201/0195 ,  H05K2201/09918 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A package substrate includes an inner interlayer, a first conductor layer on the inner interlayer, a second conductor layer on which the inner interlayer is formed, an outermost interlayer on the first conductor layer, an outermost conductor layer on the outermost interlayer and including first and second pads positioned to mount first and second electronic components on the outermost interlayer, outermost vias connecting the first and outermost conductor layers through the outermost interlayer, and skip vias connecting the outermost and second conductor layers through the outermost and inner interlayers. The first conductor layer includes a first circuit connecting two outermost vias, and the outermost conductor layer includes an outermost circuit connecting one of the two outermost vias and one skip via such that the first conductor circuit, two outermost vias, outermost circuit and one skip via form a connection path connecting one second pad and the second conductor layer.

Abstract translation: 封装基板包括内夹层，内层中的第一导体层，形成有内层的第二导体层，第一导体层上的最外层，最外层的最外层导体层， 定位成将第一和第二电子部件安装在最外层中间的第二焊盘，通过最外层间连接第一和最外层导体层的最外面通孔，以及通过最外层和内层间连接最外层和第二导体层的通孔。 第一导体层包括连接两个最外面通孔的第一电路，最外面的导体层包括连接两个最外面通孔中的一个的最外部电路和一个跳过通孔，使得第一导体电路，两个最外面的通孔，最外面的电路和一个跳过通孔 形成连接一个第二焊盘和第二导体层的连接路径。

公开(公告)号：US20150279772A1

公开(公告)日：2015-10-01

申请号：US14669393

申请日：2015-03-26

Applicant: IBIDEN CO., LTD.

Inventor： Yasushi INAGAKI ,  Yasuhiro Takahashi ,  Satoshi Kurokawa

IPC: H01L23/498 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/00 ,  H01L24/16 ,  H01L25/065 ,  H01L25/0655 ,  H01L2224/131 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/014

Abstract: A package substrate includes interlayer insulating layers including outermost and inner-layer layers, conductor layers including an outermost layer, a first layer between the outermost and inner-layer layers, and a second layer on which the inner-layer layer is formed, via conductors including first and second conductors through the outermost insulating layer, and skip via conductors through the outermost and inner-layer insulating layers to connect the outermost and second conductor layers. The outermost conductor layer includes first and second pads to mount first and second electronic components on the outermost insulating layer, the first conductors are positioned to connect the first conductor layer and first pads, the second conductors are positioned to connect the first conductor layer and second pads, and the first conductor layer has area on surface of the inner-layer insulating layer which is in range of 3 to 15% of area of the surface of the inner-layer insulating layer.

Abstract translation: 封装衬底包括包括最外层和内层层的层间绝缘层，包括最外层的导体层，最外层和内层层之间的第一层以及形成内层层的第二层，经由导体 包括穿过最外绝缘层的第一和第二导体，并且经由导体穿过最外层和内层绝缘层，以连接最外层和第二导体层。 最外面的导体层包括用于将第一和第二电子部件安装在最外绝缘层上的第一和第二焊盘，第一导体被定位成连接第一导体层和第一焊盘，第二导体定位成连接第一导体层和第二导体层 衬垫，并且第一导体层在内层绝缘层的表面上具有在内层绝缘层的表面的面积的3至15％范围内的面积。