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    METHODS AND STRUCTURE FOR CARRIER-LESS THIN WAFER HANDLING
    2.
    发明申请
    METHODS AND STRUCTURE FOR CARRIER-LESS THIN WAFER HANDLING 有权
    无载波干扰处理的方法和结构

    公开(公告)号：US20150255345A1

    公开(公告)日：2015-09-10

    申请号：US14722672

    申请日：2015-05-27

    Applicant: Invensas Corporation

    Inventor： Cyprian Emeka Uzoh ,  Pezhman Monadgemi ,  Michael Newman ,  Charles G. Woychik ,  Terrence Caskey

    IPC: H01L21/768 ,  H01L23/00 ,  H01L21/3105 ,  H01L21/78 ,  H01L21/683

    CPC classification number: H01L21/76898 ,  H01L21/31053 ,  H01L21/561 ,  H01L21/6835 ,  H01L21/768 ,  H01L21/76841 ,  H01L21/76877 ,  H01L21/78 ,  H01L23/481 ,  H01L24/94 ,  H01L2221/68327 ,  H01L2221/68381 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01L2924/00

    Abstract: Methods of forming a microelectronic assembly and the resulting structures and devices are disclosed herein. In one embodiment, a method of forming a microelectronic assembly includes removing material exposed at portions of a surface of a substrate to form a processed substrate having a plurality of thinned portions separated by integral supporting portions of the processed substrate having a thickness greater than a thickness of the thinned portions, at least some of the thinned portions including a plurality of electrically conductive interconnects extending in a direction of the thicknesses of the thinned portions and exposed at the surface; and removing the supporting portions of the substrate to sever the substrate into a plurality of individual thinned portions, at least some individual thinned portions including the interconnects.

    Abstract translation: 本文公开了形成微电子组件的方法以及所得到的结构和装置。 在一个实施例中，形成微电子组件的方法包括去除在衬底的表面的部分处暴露的材料，以形成经处理的衬底，该衬底具有多个由处理衬底的整体支撑部分分离的薄化部分，该部分厚度大于厚度 减薄部分中的至少一些薄化部分包括在薄壁部分的厚度方向上延伸并在表面露出的多个导电互连件; 以及去除衬底的支撑部分以将衬底切割成多个单独的薄化部分，至少一些单独的变薄部分，包括互连。

    METHOD OF PROCESSING A DEVICE SUBSTRATE
    4.
    发明申请
    METHOD OF PROCESSING A DEVICE SUBSTRATE 有权
    处理器件基板的方法

    公开(公告)号：US20140315384A1

    公开(公告)日：2014-10-23

    申请号：US14323329

    申请日：2014-07-03

    Applicant: Invensas Corporation

    Inventor： Pezhman Monadgemi

    IPC: H01L23/00 ,  H01L21/304

    CPC classification number: H01L23/562 ,  H01L21/304 ,  H01L21/31133 ,  H01L21/76898 ,  H01L21/78 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods of processing a device substrate are disclosed herein. In one embodiment, a method of processing a device substrate can include bonding a first surface of a device substrate to a carrier with a polymeric material. The device substrate may have a plurality of first openings extending from the first surface towards a second surface of the device substrate opposite from the first surface. Then, material can be removed at the second surface of the device substrate, wherein at least some of the first openings communicate with the second surface at least one of before or after performing the removal of the material. Then, at least a portion of the polymeric material disposed between the first surface and the carrier substrate can be exposed to a substance through at least some first openings to debond the device substrate from the carrier substrate.

    Abstract translation: 本文公开了处理器件衬底的方法。 在一个实施例中，处理器件衬底的方法可以包括将器件衬底的第一表面与聚合物材料接合到载体上。 器件衬底可以具有多个第一开口，从第一表面延伸到与第一表面相对的器件衬底的第二表面。 然后，可以在器件基板的第二表面处去除材料，其中至少一些第一开口在进行材料去除之前或之后与第二表面连通。 然后，设置在第一表面和载体衬底之间的聚合物材料的至少一部分可以通过至少一些第一开口暴露于物质，以使器件衬底从载体衬底脱离。

    METHOD AND STRUCTURES FOR HEAT DISSIPATING INTERPOSERS
    5.
    发明申请
    METHOD AND STRUCTURES FOR HEAT DISSIPATING INTERPOSERS 有权
    热交换器的方法和结构

    公开(公告)号：US20140167267A1

    公开(公告)日：2014-06-19

    申请号：US13720346

    申请日：2012-12-19

    Applicant: INVENSAS CORPORATION

    Inventor： Cyprian Emeka Uzoh ,  Pezhman Monadgemi ,  Terrence Caskey ,  Fatima Lina Ayatollahi ,  Belgacem Haba ,  Charles G. Woychik ,  Michael Newman

    IPC: H01L23/532 ,  H01L23/488 ,  H01L21/768

    CPC classification number: H01L23/49827 ,  H01L21/76829 ,  H01L21/76898 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/49866 ,  H01L2924/00 ,  H01L2924/0002

    Abstract: A method for making an interconnect element includes depositing a thermally conductive layer on an in-process unit. The in-process unit includes a semiconductor material layer defining a surface and edges surrounding the surface, a plurality of conductive elements, each conductive element having a first portion extending through the semiconductor material layer and a second portion extending from the surface of the semiconductor material layer. Dielectric coatings extend over at least the second portion of each conductive element. The thermally conductive layer is deposited on the in-process unit at a thickness of at least 10 microns so as to overlie a portion of the surface of the semiconductor material layer between the second portions of the conductive elements with the dielectric coatings positioned between the conductive elements and the thermally conductive layer.

    Abstract translation: 制造互连元件的方法包括将热传导层沉积在处理单元上。 处理单元包括限定表面和围绕表面的边缘的半导体材料层，多个导电元件，每个导电元件具有延伸穿过半导体材料层的第一部分和从半导体材料的表面延伸的第二部分 层。 电介质涂层至少延伸到每个导电元件的第二部分。 导热层以至少10微米的厚度沉积在处理单元上，以覆盖在导电元件的第二部分之间的半导体材料层的表面的一部分，其中介电涂层位于导电 元件和导热层。

    CARRIER-LESS SILICON INTERPOSER
    9.
    发明申请
    CARRIER-LESS SILICON INTERPOSER 审中-公开
    无载体硅介质

    公开(公告)号：US20160079090A1

    公开(公告)日：2016-03-17

    申请号：US14950180

    申请日：2015-11-24

    Applicant: Invensas Corporation

    Inventor： Michael Newman ,  Cyprian Uzoh ,  Charles G. Woychik ,  Pezhman Monadgemi ,  Terrence Caskey

    IPC: H01L21/48 ,  H05K3/00

    CPC classification number: H01L21/486 ,  H01L23/147 ,  H01L23/49827 ,  H01L2224/13 ,  H01L2224/16225 ,  H05K1/111 ,  H05K3/0014 ,  H05K3/4038 ,  Y10T29/49117

    Abstract: An interposer has conductive elements at a first side and terminals at a second side opposite therefrom, for connecting with a microelectronic element and a second component, respectively. The component includes a first element having a thermal expansion coefficient less than 10 ppm/° C., and an insulating second element, with a plurality of openings extending from the second side through the second element towards the first element. A conductive structure extending through the openings in the second element and through the first element electrically connects the terminals with the conductive elements.

    Abstract translation: 插入件在第一侧具有导电元件，在与其相对的第二侧具有端子，用于分别与微电子元件和第二元件连接。 该组件包括具有小于10ppm /℃的热膨胀系数的第一元件和绝缘的第二元件，多个开口从第二侧延伸穿过第二元件朝向第一元件。 延伸穿过第二元件中的开口并通过第一元件的导电结构将端子与导电元件电连接。

    Method and structures for heat dissipating interposers
    10.
    发明授权
    Method and structures for heat dissipating interposers 有权
    散热插件的方法和结构

    公开(公告)号：US09123780B2

    公开(公告)日：2015-09-01

    申请号：US13720346

    申请日：2012-12-19

    Applicant: Invensas Corporation

    Inventor： Cyprian Emeka Uzoh ,  Pezhman Monadgemi ,  Terrence Caskey ,  Fatima Lina Ayatollahi ,  Belgacem Haba ,  Charles G. Woychik ,  Michael Newman

    IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/36 ,  H01L23/367

    CPC classification number: H01L23/49827 ,  H01L21/76829 ,  H01L21/76898 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/49866 ,  H01L2924/00 ,  H01L2924/0002

    Abstract: A method for making an interconnect element includes depositing a thermally conductive layer on an in-process unit. The in-process unit includes a semiconductor material layer defining a surface and edges surrounding the surface, a plurality of conductive elements, each conductive element having a first portion extending through the semiconductor material layer and a second portion extending from the surface of the semiconductor material layer. Dielectric coatings extend over at least the second portion of each conductive element. The thermally conductive layer is deposited on the in-process unit at a thickness of at least 10 microns so as to overlie a portion of the surface of the semiconductor material layer between the second portions of the conductive elements with the dielectric coatings positioned between the conductive elements and the thermally conductive layer.

    Abstract translation: 制造互连元件的方法包括将热传导层沉积在处理单元上。 处理单元包括限定表面和围绕表面的边缘的半导体材料层，多个导电元件，每个导电元件具有延伸穿过半导体材料层的第一部分和从半导体材料的表面延伸的第二部分 层。 电介质涂层至少延伸到每个导电元件的第二部分。 导热层以至少10微米的厚度沉积在处理单元上，以覆盖在导电元件的第二部分之间的半导体材料层的表面的一部分，其中介电涂层位于导电 元件和导热层。

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