公开(公告)号：US20220165703A1

公开(公告)日：2022-05-26

申请号：US17512123

申请日：2021-10-27

Applicant: Invensas Corporation

Inventor： Ellis Chau ,  Reynaldo Co ,  Roseann Alatorre ,  Philip Damberg ,  Wei-Shun Wang ,  Se Young Yang

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L23/495 ,  H01L21/48 ,  H01L23/367 ,  H01L23/433

Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

公开(公告)号：US10756049B2

公开(公告)日：2020-08-25

申请号：US15699288

申请日：2017-09-08

Applicant: Invensas Corporation

Inventor： Ellis Chau ,  Reynaldo Co ,  Roseann Alatorre ,  Philip Damberg ,  Wei-Shun Wang ,  Se Young Yang

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L23/495 ,  H01L21/48 ,  H01L23/367 ,  H01L23/433 ,  H01L25/065 ,  H05K3/34

Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

公开(公告)号：US09508689B2

公开(公告)日：2016-11-29

申请号：US14871185

申请日：2015-09-30

Applicant: Invensas Corporation

Inventor： Reynaldo Co ,  Jeffrey S. Leal ,  Suzette K. Pangrle ,  Scott McGrath ,  De Ann Eileen Melcher ,  Keith L. Barrie ,  Grant Villavicencio ,  Elmer M. Del Rosario ,  John R. Bray

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L25/00 ,  H01L21/78

CPC classification number: H01L25/0657 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3171 ,  H01L23/3185 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/18 ,  H01L24/24 ,  H01L24/82 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2224/0235 ,  H01L2224/02371 ,  H01L2224/03002 ,  H01L2224/03318 ,  H01L2224/0332 ,  H01L2224/03632 ,  H01L2224/03848 ,  H01L2224/05016 ,  H01L2224/05017 ,  H01L2224/0529 ,  H01L2224/05553 ,  H01L2224/24051 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82102 ,  H01L2224/94 ,  H01L2225/06551 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/00 ,  H01L2224/03

Abstract: Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spots. Also, die pad to z-interconnect connectors formed by the methods, and shaped and dimensioned accordingly. Also, stacked die assemblies and stacked die packages containing die prepared according to the methods and having die pad to z-interconnect connectors formed by the methods and shaped and dimensioned accordingly.

公开(公告)号：US20150255424A1

公开(公告)日：2015-09-10

申请号：US14718719

申请日：2015-05-21

Applicant: Invensas Corporation

Inventor： Ellis Chau ,  Reynaldo Co ,  Roseann Alatorre ,  Philip Damberg ,  Wei-Shun Wang ,  Se Young Yang

IPC: H01L23/00 ,  H01L21/56

CPC classification number: H01L24/85 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49517 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/16 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/45565 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48997 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/851 ,  H01L2224/8518 ,  H01L2224/85399 ,  H01L2224/85951 ,  H01L2224/85986 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1715 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/1053 ,  Y10T29/49149 ,  Y10T29/49151 ,  H01L2224/45664 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076

Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

Abstract translation: 微电子封装包括具有第一表面的衬底。 微电子元件覆盖在第一表面上。 导电元件在衬底的第一表面处露出，其中至少一些电连接到微电子元件。 封装包括引线键合，其具有接合到相应导电元件的底部和远离基板的远离基座的端部。 线接合的端部限定在引线接合的尖端处，并且引线键合限定了基部和其尖端之间的相应的第一直径。 尖端具有至少一个尺寸小于引线接合的相应第一直径。 电介质封装层覆盖引线接合的部分，并且引线键合的未封装部分由引线键合的部分限定，包括末端，被封装层覆盖。

公开(公告)号：US08878353B2

公开(公告)日：2014-11-04

申请号：US13722189

申请日：2012-12-20

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Ilyas Mohammed ,  Terrence Caskey ,  Reynaldo Co ,  Ellis Chau

IPC: H01L23/02 ,  H01L21/00 ,  H05K1/18 ,  H01L23/00 ,  H01L23/528

CPC classification number: H05K1/11 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/528 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/10126 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1191 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13101 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14135 ,  H01L2224/16105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/32225 ,  H01L2224/45012 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45101 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45624 ,  H01L2224/45655 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15322 ,  H01L2924/181 ,  H01L2924/19107 ,  H05K1/0298 ,  H05K1/181 ,  H05K1/185 ,  H05K2201/10515 ,  H05K2201/10977 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: A structure may include bond elements having bases joined to conductive elements at a first portion of a first surface and end surfaces remote from the substrate. A dielectric encapsulation element may overlie and extend from the first portion and fill spaces between the bond elements to separate the bond elements from one another. The encapsulation element has a third surface facing away from the first surface. Unencapsulated portions of the bond elements are defined by at least portions of the end surfaces uncovered by the encapsulation element at the third surface. The encapsulation element at least partially defines a second portion of the first surface that is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some conductive elements are at the second portion and configured for connection with such microelectronic element.

Abstract translation: 结构可以包括在第一表面的第一部分和远离基底的端表面处具有连接到导电元件的基底的结合元件。 电介质封装元件可以从第一部分覆盖并延伸并填充接合元件之间的空间，以将接合元件彼此分开。 封装元件具有背离第一表面的第三表面。 粘合元件的未封装部分由在第三表面处被封装元件未覆盖的至少部分端面限定。 封装元件至少部分地限定除了第一部分之外的第一表面的第二部分，并且具有尺寸适于容纳微电子元件的整个区域的区域。 一些导电元件位于第二部分并被配置为与这种微电子元件连接。

公开(公告)号：US20140036454A1

公开(公告)日：2014-02-06

申请号：US13795756

申请日：2013-03-12

Applicant: INVENSAS CORPORATION

Inventor： Terrence Caskey ,  Ilyas Mohammed ,  Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Michael Newman ,  Pezhman Monadgemi ,  Reynaldo Co ,  Ellis Chau ,  Belgacem Haba

IPC: H05K1/02 ,  H05K3/46

CPC classification number: H01L25/105 ,  H01L21/486 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/02379 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45664 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/381 ,  H05K1/0298 ,  H05K3/46 ,  Y10T29/49126 ,  Y10T29/49162 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds.

Abstract translation: 制造插入件的方法包括形成结合到第一元件的一个或多个第一表面的多个引线键合。 形成电介质封装，其接触将引线接合部彼此分隔开的引线接合的边缘表面。 进一步的处理包括去除第一元件的至少一部分，其中插入件具有通过至少封装相互隔开的第一和第二相对侧，并且插入件分别在第一和第二相对侧具有第一接触和第二接触， 分别与第一和第二部件电连接，第一触点通过引线键与第二触点电连接。

公开(公告)号：US20130200533A1

公开(公告)日：2013-08-08

申请号：US13795811

申请日：2013-03-12

Applicant: Invensas Corporation

Inventor： Ellis Chau ,  Reynaldo Co ,  Roseann Alatorre ,  Philip Damberg ,  Wei-Shun Wang ,  Se Young Yang

IPC: H01L23/00

CPC classification number: H01L24/85 ,  H01L21/4853 ,  H01L21/56 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/49517 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/06 ,  H01L24/16 ,  H01L24/43 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/78 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4554 ,  H01L2224/45565 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48997 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/851 ,  H01L2224/8518 ,  H01L2224/85399 ,  H01L2224/85951 ,  H01L2224/85986 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1029 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1715 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/3511 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/1053 ,  Y10T29/49149 ,  Y10T29/49151 ,  H01L2224/45664 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076

Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

公开(公告)号：US11189595B2

公开(公告)日：2021-11-30

申请号：US16999601

申请日：2020-08-21

Applicant: Invensas Corporation

Inventor： Ellis Chau ,  Reynaldo Co ,  Roseann Alatorre ,  Philip Damberg ,  Wei-Shun Wang ,  Se Young Yang

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L25/10 ,  H01L25/00 ,  H01L23/495 ,  H01L21/48 ,  H01L23/367 ,  H01L23/433 ,  H01L25/065 ,  H05K3/34

Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

公开(公告)号：US09893033B2

公开(公告)日：2018-02-13

申请号：US15096588

申请日：2016-04-12

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Reynaldo Co ,  Rizza Lee Saga Cizek ,  Wael Zohni

IPC: B23K31/02 ,  H01L23/00 ,  B23K20/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L24/85 ,  B23K20/004 ,  B23K20/005 ,  B23K20/007 ,  H01L21/4853 ,  H01L21/56 ,  H01L23/49811 ,  H01L24/43 ,  H01L24/78 ,  H01L2224/04105 ,  H01L2224/056 ,  H01L2224/432 ,  H01L2224/4382 ,  H01L2224/43985 ,  H01L2224/783 ,  H01L2224/78301 ,  H01L2224/7855 ,  H01L2224/78621 ,  H01L2224/78822 ,  H01L2224/85 ,  H01L2224/85345 ,  H01L2224/85399 ,  H01L2224/96 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/2064 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: An electrically conductive lead is formed using a bonding tool. After bonding the wire to a metal surface and extending a length of the wire beyond the bonding tool, the wire is clamped. Movement of the bonding tool imparts a kink to the wire at a location where the wire is fully separated from any metal element other than the bonding tool. A forming element, e.g., an edge or a blade skirt provided at an exterior surface of the bonding tool can help kink the wire. Optionally, twisting the wire while tensioning the wire using the bonding tool can cause the wire to break and define an end. The lead then extends from the metal surface to the end, and may exhibit a sign of the torsional force applied thereto.

公开(公告)号：US09825002B2

公开(公告)日：2017-11-21

申请号：US15208985

申请日：2016-07-13

Applicant: Invensas Corporation

Inventor： Rajesh Katkar ,  Reynaldo Co ,  Scott McGrath ,  Ashok S. Prabhu ,  Sangil Lee ,  Liang Wang ,  Hong Shen

IPC: H01L21/56 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/02335 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83005 ,  H01L2224/9222 ,  H01L2225/06506 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2225/06596 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/1032 ,  H01L2924/10329 ,  H01L2924/1037 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/18162 ,  H01L2924/19107 ,  H01L2224/19

Abstract: A microelectronic assembly includes a stack of semiconductor chips each having a front surface defining a respective plane of a plurality of planes. A chip terminal may extend from a contact at a front surface of each chip in a direction towards the edge surface of the respective chip. The chip stack is mounted to substrate at an angle such that edge surfaces of the chips face a major surface of the substrate that defines a second plane that is transverse to, i.e., not parallel to the plurality of parallel planes. An electrically conductive material electrically connects the chip terminals with corresponding substrate contacts.