公开(公告)号：US09893030B2

公开(公告)日：2018-02-13

申请号：US15212603

申请日：2016-07-18

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Belgacem Haba ,  Charles G. Woychik ,  Michael Newman ,  Terrence Caskey

IPC: H05K7/00 ,  H01L23/00 ,  H05K1/18 ,  H05K3/30 ,  H01L25/065 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L24/13 ,  H01L21/563 ,  H01L23/564 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/03912 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05557 ,  H01L2224/05568 ,  H01L2224/05571 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05664 ,  H01L2224/10145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/1147 ,  H01L2224/11903 ,  H01L2224/13024 ,  H01L2224/13025 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/1319 ,  H01L2224/14517 ,  H01L2224/1601 ,  H01L2224/16057 ,  H01L2224/16058 ,  H01L2224/16104 ,  H01L2224/16105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16503 ,  H01L2224/17505 ,  H01L2224/17517 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81001 ,  H01L2224/81007 ,  H01L2224/811 ,  H01L2224/81139 ,  H01L2224/8192 ,  H01L2224/83104 ,  H01L2224/9201 ,  H01L2224/9212 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00014 ,  H05K1/181 ,  H05K3/30 ,  Y10T29/4913 ,  H01L2924/00012 ,  H01L2924/01015 ,  H01L2924/01074 ,  H01L2224/05552

Abstract: Microelectronic assemblies and methods for making the same are disclosed herein. In one embodiment, a method of forming a microelectronic assembly comprises assembling first and second components to have first major surfaces of the first and second components facing one another and spaced apart from one another by a predetermined spacing, the first component having first and second oppositely-facing major surfaces, a first thickness extending in a first direction between the first and second major surfaces, and a plurality of first metal connection elements at the first major surface, the second component having a plurality of second metal connection elements at the first major surface of the second component; and plating a plurality of metal connector regions each connecting and extending continuously between a respective first connection element and a corresponding second connection element opposite the respective first connection element in the first direction.

公开(公告)号：US09601398B2

公开(公告)日：2017-03-21

申请号：US14500858

申请日：2014-09-29

Applicant: Invensas Corporation

Inventor： Charles G. Woychik ,  Se Young Yang ,  Pezhman Monadgemi ,  Terrence Caskey ,  Cyprian Emeka Uzoh

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/498 ,  G01R31/28 ,  H01L21/683 ,  H01L25/04 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L22/32 ,  G01R31/2886 ,  H01L21/6835 ,  H01L22/14 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/04 ,  H01L25/0652 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/11015 ,  H01L2224/11849 ,  H01L2224/13014 ,  H01L2224/13082 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/16111 ,  H01L2224/16112 ,  H01L2224/16146 ,  H01L2224/16147 ,  H01L2224/16237 ,  H01L2224/16257 ,  H01L2224/16267 ,  H01L2224/16503 ,  H01L2224/17051 ,  H01L2224/8109 ,  H01L2224/81138 ,  H01L2224/8114 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/12 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/81805

Abstract: A method of attaching a microelectronic element to a substrate can include aligning the substrate with a microelectronic element, the microelectronic element having a plurality of spaced-apart electrically conductive bumps each including a bond metal, and reflowing the bumps. The bumps can be exposed at a front surface of the microelectronic element. The substrate can have a plurality of spaced-apart recesses extending from a first surface thereof. The recesses can each have at least a portion of one or more inner surfaces that are non-wettable by the bond metal of which the bumps are formed. The reflowing of the bumps can be performed so that at least some of the bond metal of each bump liquefies and flows at least partially into one of the recesses and solidifies therein such that the reflowed bond material in at least some of the recesses mechanically engages the substrate.

公开(公告)号：US09502390B2

公开(公告)日：2016-11-22

申请号：US13795756

申请日：2013-03-12

Applicant: Invensas Corporation

Inventor： Terrence Caskey ,  Ilyas Mohammed ,  Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Michael Newman ,  Pezhman Monadgemi ,  Reynaldo Co ,  Ellis Chau ,  Belgacem Haba

IPC: H05K1/02 ,  H01L25/10 ,  H05K3/46 ,  H01L21/48 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/105 ,  H01L21/486 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0655 ,  H01L2224/02379 ,  H01L2224/04042 ,  H01L2224/16225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45664 ,  H01L2224/48091 ,  H01L2224/48108 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73257 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/381 ,  H05K1/0298 ,  H05K3/46 ,  Y10T29/49126 ,  Y10T29/49162 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds.

Abstract translation: 制造插入件的方法包括形成结合到第一元件的一个或多个第一表面的多个引线键合。 形成电介质封装，其接触将引线接合部彼此分隔开的引线接合的边缘表面。 进一步的处理包括去除第一元件的至少一部分，其中插入件具有通过至少封装相互隔开的第一和第二相对侧，并且插入件分别在第一和第二相对侧具有第一接触和第二接触， 分别与第一和第二部件电连接，第一触点通过引线键与第二触点电连接。

公开(公告)号：US09349669B2

公开(公告)日：2016-05-24

申请号：US14643264

申请日：2015-03-10

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Terrence Caskey ,  Kishor V. Desai ,  Huailiang Wei ,  Craig Mitchell ,  Belgacem Haba

IPC: H01L21/44 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/34 ,  H01L21/768 ,  H01L23/00 ,  H01L23/14 ,  H01L23/498

CPC classification number: H01L23/34 ,  H01L21/76841 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/10 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/1134 ,  H01L2224/1147 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13184 ,  H01L2224/13565 ,  H01L2224/32105 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/07811 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/81805

Abstract: A microelectronic component with circuitry includes a substrate (possibly semiconductor) having an opening in a top surface. The circuitry includes a conductive via (possibly metal) in the opening. The opening has a first sidewall of a first material, and the conductive via has a second sidewall of a second material (possibly metal). At least at one side of the opening, the first and second sidewalls are spaced from each other at the top surface of the substrate but the first and second sidewalls meet below the top surface of the substrate at a meeting location. Between the meeting location and the top surface of the substrate, the first and second sidewalls are separated by a third material (possibly foam) which is a dielectric different from the first material. The third material lowers thermal stress in case of thermal expansion compared to a structure in which the third material were replaced with the second material.

Abstract translation: 具有电路的微电子部件包括在顶表面具有开口的衬底（可能的半导体）。 电路包括开口中的导电通孔（可能是金属）。 开口具有第一材料的第一侧壁，并且导电通孔具有第二材料（可能是金属）的第二侧壁。 至少在开口的一侧，第一和第二侧壁在基板的顶表面处彼此间隔开，但是第一和第二侧壁在会议位置处在基板的顶表面下面相交。 在会议位置和基板的顶表面之间，第一和第二侧壁由不同于第一材料的电介质的第三材料（可能是泡沫）隔开。 第三种材料与第三种材料被第二种材料替换的结构相比，在热膨胀的情况下降低了热应力。

公开(公告)号：US20160079090A1

公开(公告)日：2016-03-17

申请号：US14950180

申请日：2015-11-24

Applicant: Invensas Corporation

Inventor： Michael Newman ,  Cyprian Uzoh ,  Charles G. Woychik ,  Pezhman Monadgemi ,  Terrence Caskey

IPC: H01L21/48 ,  H05K3/00

CPC classification number: H01L21/486 ,  H01L23/147 ,  H01L23/49827 ,  H01L2224/13 ,  H01L2224/16225 ,  H05K1/111 ,  H05K3/0014 ,  H05K3/4038 ,  Y10T29/49117

Abstract: An interposer has conductive elements at a first side and terminals at a second side opposite therefrom, for connecting with a microelectronic element and a second component, respectively. The component includes a first element having a thermal expansion coefficient less than 10 ppm/° C., and an insulating second element, with a plurality of openings extending from the second side through the second element towards the first element. A conductive structure extending through the openings in the second element and through the first element electrically connects the terminals with the conductive elements.

Abstract translation: 插入件在第一侧具有导电元件，在与其相对的第二侧具有端子，用于分别与微电子元件和第二元件连接。 该组件包括具有小于10ppm /℃的热膨胀系数的第一元件和绝缘的第二元件，多个开口从第二侧延伸穿过第二元件朝向第一元件。 延伸穿过第二元件中的开口并通过第一元件的导电结构将端子与导电元件电连接。

公开(公告)号：US09123780B2

公开(公告)日：2015-09-01

申请号：US13720346

申请日：2012-12-19

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Pezhman Monadgemi ,  Terrence Caskey ,  Fatima Lina Ayatollahi ,  Belgacem Haba ,  Charles G. Woychik ,  Michael Newman

IPC: H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/36 ,  H01L23/367

CPC classification number: H01L23/49827 ,  H01L21/76829 ,  H01L21/76898 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/3736 ,  H01L23/481 ,  H01L23/49838 ,  H01L23/49866 ,  H01L2924/00 ,  H01L2924/0002

Abstract: A method for making an interconnect element includes depositing a thermally conductive layer on an in-process unit. The in-process unit includes a semiconductor material layer defining a surface and edges surrounding the surface, a plurality of conductive elements, each conductive element having a first portion extending through the semiconductor material layer and a second portion extending from the surface of the semiconductor material layer. Dielectric coatings extend over at least the second portion of each conductive element. The thermally conductive layer is deposited on the in-process unit at a thickness of at least 10 microns so as to overlie a portion of the surface of the semiconductor material layer between the second portions of the conductive elements with the dielectric coatings positioned between the conductive elements and the thermally conductive layer.

Abstract translation: 制造互连元件的方法包括将热传导层沉积在处理单元上。 处理单元包括限定表面和围绕表面的边缘的半导体材料层，多个导电元件，每个导电元件具有延伸穿过半导体材料层的第一部分和从半导体材料的表面延伸的第二部分 层。 电介质涂层至少延伸到每个导电元件的第二部分。 导热层以至少10微米的厚度沉积在处理单元上，以覆盖在导电元件的第二部分之间的半导体材料层的表面的一部分，其中介电涂层位于导电 元件和导热层。

公开(公告)号：US09095074B2

公开(公告)日：2015-07-28

申请号：US14517268

申请日：2014-10-17

Applicant: Invensas Corporation

Inventor： Belgacem Haba ,  Ilyas Mohammed ,  Terrence Caskey ,  Reynaldo Co ,  Ellis Chau

IPC: H01L23/48 ,  H01L21/00 ,  H05K1/18 ,  H01L23/528 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/10 ,  H01L25/03 ,  H01L21/56 ,  H01L23/00

CPC classification number: H05K1/11 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3157 ,  H01L23/49811 ,  H01L23/528 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/10126 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1191 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13101 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14135 ,  H01L2224/16105 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/32225 ,  H01L2224/45012 ,  H01L2224/45014 ,  H01L2224/45015 ,  H01L2224/45101 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/45624 ,  H01L2224/45655 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/15322 ,  H01L2924/181 ,  H01L2924/19107 ,  H05K1/0298 ,  H05K1/181 ,  H05K1/185 ,  H05K2201/10515 ,  H05K2201/10977 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/014

Abstract: A structure may include bond elements having bases joined to conductive elements at a first portion of a first surface and end surfaces remote from the substrate. A dielectric encapsulation element may overlie and extend from the first portion and fill spaces between the bond elements to separate the bond elements from one another. The encapsulation element has a third surface facing away from the first surface. Unencapsulated portions of the bond elements are defined by at least portions of the end surfaces uncovered by the encapsulation element at the third surface. The encapsulation element at least partially defines a second portion of the first surface that is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some conductive elements are at the second portion and configured for connection with such microelectronic element.

Abstract translation: 结构可以包括在第一表面的第一部分和远离基底的端表面处具有连接到导电元件的基底的结合元件。 电介质封装元件可以从第一部分覆盖并延伸并填充接合元件之间的空间，以将接合元件彼此分开。 封装元件具有背离第一表面的第三表面。 粘合元件的未封装部分由在第三表面处被封装元件未覆盖的至少部分端面限定。 封装元件至少部分地限定除了第一部分之外的第一表面的第二部分，并且具有尺寸适于容纳微电子元件的整个区域的区域。 一些导电元件位于第二部分并被配置为与这种微电子元件连接。

公开(公告)号：US20150162241A1

公开(公告)日：2015-06-11

申请号：US14627252

申请日：2015-02-20

Applicant: INVENSAS CORPORATION

Inventor： Cyprian Emeka Uzoh ,  Charles G. Woychik ,  Michael Newman ,  Pezhman Monadgemi ,  Terrence Caskey

IPC: H01L21/768 ,  H01L21/3205 ,  H01L23/532

CPC classification number: H01L21/76877 ,  H01L21/32055 ,  H01L21/76802 ,  H01L21/76841 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/525 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures and methods of forming the same are disclosed herein. In one embodiment, a structure can comprise a region having first and second oppositely facing surfaces. A barrier region can overlie the region. An alloy region can overlie the barrier region. The alloy region can include a first metal and one or more elements selected from the group consisting of silicon (Si), germanium (Ge), indium (Id), boron (B), arsenic (As), antimony (Sb), tellurium (Te), or cadmium (Cd).

Abstract translation: 本文公开了其形成的结构和方法。 在一个实施例中，结构可以包括具有第一和第二相对面的表面的区域。 屏障区域可以覆盖该区域。 合金区域可以覆盖阻挡区域。 合金区域可以包括第一金属和选自硅（Si），锗（Ge），铟（Id），硼（B），砷（As），锑（Sb），碲的一种或多种元素 （Te）或镉（Cd）。

公开(公告)号：US08981564B2

公开(公告)日：2015-03-17

申请号：US13897956

申请日：2013-05-20

Applicant: Invensas Corporation

Inventor： Charles G. Woychik ,  Cyprian Emeka Uzoh ,  Michael Newman ,  Pezhman Monadgemi ,  Terrence Caskey

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76877 ,  H01L21/32055 ,  H01L21/76802 ,  H01L21/76841 ,  H01L21/76858 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L23/525 ,  H01L23/53233 ,  H01L23/53238 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures and methods of forming the same are disclosed herein. In one embodiment, a structure can comprise a region having first and second oppositely facing surfaces. A barrier region can overlie the region. An alloy region can overlie the barrier region. The alloy region can include a first metal and one or more elements selected from the group consisting of silicon (Si), germanium (Ge), indium (Id), boron (B), arsenic (As), antimony (Sb), tellurium (Te), or cadmium (Cd).

Abstract translation: 本文公开了其形成的结构和方法。 在一个实施例中，结构可以包括具有第一和第二相对面的表面的区域。 屏障区域可以覆盖该区域。 合金区域可以覆盖阻挡区域。 合金区域可以包括第一金属和选自硅（Si），锗（Ge），铟（Id），硼（B），砷（As），锑（Sb），碲的一种或多种元素 （Te）或镉（Cd）。

公开(公告)号：US10475733B2

公开(公告)日：2019-11-12

申请号：US16156595

申请日：2018-10-10

Applicant: Invensas Corporation

Inventor： Cyprian Emeka Uzoh ,  Pezhman Monadgemi ,  Terrence Caskey ,  Fatima Lina Ayatollahi ,  Belgacem Haba ,  Charles G. Woychik ,  Michael Newman

IPC: H05K1/09 ,  H05K1/11 ,  H05K3/38 ,  H01L21/02 ,  H01L21/48 ,  H01L23/52 ,  H01L23/522 ,  H01L23/532 ,  H01L23/498 ,  H01L21/768 ,  H01L23/373 ,  H01L23/367 ,  H01L23/48 ,  H01L23/36

Abstract: An interconnect element includes a semiconductor or insulating material layer that has a first thickness and defines a first surface; a thermally conductive layer; a plurality of conductive elements; and a dielectric coating. The thermally conductive layer includes a second thickness of at least 10 microns and defines a second surface of the interconnect element. The plurality of conductive elements extend from the first surface of the interconnect element to the second surface of the interconnect element. The dielectric coating is between at least a portion of each conductive element and the thermally conductive layer.