公开(公告)号：US07843051B2

公开(公告)日：2010-11-30

申请号：US12212566

申请日：2008-09-17

申请人： In-Sang Song ,  In-Ku Kang ,  Kyung-Man Kim

发明人： In-Sang Song ,  In-Ku Kang ,  Kyung-Man Kim

IPC分类号： H01L23/02

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1064 ,  H01L2924/01087 ,  H01L2924/00014

摘要： Provided are a semiconductor device and a method of fabricating the same, and more particularly, a semiconductor package and a method of fabricating the semiconductor package. The semiconductor package includes a first package that comprises a first substrate, at least one first semiconductor chip stacked on the first substrate, and first conductive pads exposed on a top surface of the first substrate; a second package disposed below the first package such that the second package comprises a second substrate, at least one second semiconductor chip, and second conductive pads exposed on a bottom surface of the second substrate; and a connection unit that extends from the first conductive pads to the second conductive pads such that the connection unit covers a side surface of the first package and a side surface of the second package in order to electrically connect the first package to the second package.

摘要翻译： 提供一种半导体器件及其制造方法，更具体地，涉及一种半导体封装以及半导体封装的制造方法。 半导体封装包括第一封装，其包括第一衬底，堆叠在第一衬底上的至少一个第一半导体芯片和暴露在第一衬底的顶表面上的第一导电焊盘; 设置在所述第一封装下方的第二封装，使得所述第二封装包括第二衬底，至少一个第二半导体芯片和暴露在所述第二衬底的底表面上的第二导电焊盘; 以及连接单元，其从所述第一导电焊盘延伸到所述第二导电焊盘，使得所述连接单元覆盖所述第一封装的侧表面和所述第二封装的侧表面，以将所述第一封装电连接到所述第二封装。

公开(公告)号：US07371675B2

公开(公告)日：2008-05-13

申请号：US10968915

申请日：2004-10-21

申请人： In-Ku Kang ,  Sang-Ho An ,  Sun-Mo Yang

发明人： In-Ku Kang ,  Sang-Ho An ,  Sun-Mo Yang

IPC分类号： H01L21/44

CPC分类号： H01L24/85 ,  H01L24/03 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/78 ,  H01L25/0657 ,  H01L2224/03 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/1134 ,  H01L2224/32145 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48451 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/48599 ,  H01L2224/4903 ,  H01L2224/49051 ,  H01L2224/78301 ,  H01L2224/85051 ,  H01L2224/8518 ,  H01L2224/85186 ,  H01L2224/85986 ,  H01L2225/0651 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20651 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/00015 ,  H01L2224/4554 ,  H01L2224/85399

摘要： A method and apparatus for bonding a wire and a wire bond device formed by the same are disclosed. The method includes providing a carrier with at least a first pad, providing a semiconductor chip having at least the second pad, the at least second pad being smaller than the first a pad, forming a conductive stud bump on the second pad, and forming a bonding wire that has two terminal portions, which are respectively bonded to the first pad and the stud bump to electrically connect the first pad and the second pad. The stud bump is bonded to the second pad by a ball bonding method which uses a wire that has an approximately smaller diameter than the bonding wire. Further, a prominence formed on one end of the terminal portions is provided which has an approximately larger diameter than the stud bump.

摘要翻译： 公开了一种用于接合线的方法和装置以及由其形成的引线接合装置。 该方法包括向载体提供至少第一焊盘，提供具有至少第二焊盘的至少第二焊盘的至少第二焊盘小于第一焊盘的半导体芯片，在第二焊盘上形成导电突起凸块，并形成 接合线，其具有分别接合到第一焊盘和柱形凸起的两个端子部分，以电连接第一焊盘和第二焊盘。 通过使用具有比接合线大致小的直径的导线的球接合方法将柱形凸起接合到第二垫。 此外，提供形成在端子部分的一端上的凸起，其具有比螺柱凸块大得多的直径。

公开(公告)号：US07067413B2

公开(公告)日：2006-06-27

申请号：US10885769

申请日：2004-07-08

申请人： Jin-Ho Kim ,  In-Ku Kang ,  Sang-Yeop Lee

发明人： Jin-Ho Kim ,  In-Ku Kang ,  Sang-Yeop Lee

IPC分类号： H01L21/44

CPC分类号： H01L24/85 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L2224/02126 ,  H01L2224/02166 ,  H01L2224/05554 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4809 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48472 ,  H01L2224/48479 ,  H01L2224/48599 ,  H01L2224/48699 ,  H01L2224/78301 ,  H01L2224/85045 ,  H01L2224/85051 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/85951 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/4554 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A method of wire bonding, a semiconductor chip, and a semiconductor package provides stitch-stitch bonds of a wire on a bond pad of a chip as well as on a bond position of a substrate. A ball-stitch bump is formed on an end of the wire extending from a capillary or provided on the bond pad of the chip. A ball-stitch bump is formed on the bond pad of the chip by pressing down the ball of the wire on the bond pad. A ball-stitch stitch bond of the wire is formed on the ball-stitch bump by pressing down the wire on the ball-stitch bump. The capillary is moved from the bond pad to the bond position, while loosening the wire. A stitch bond of the wire is formed on the bond position by pressing down the wire on the bond position, and then separated from the wire within the capillary. The method of wire bonding, a semiconductor chip, and a semiconductor package can reduce or minimize a moving path of the capillary and provide more effective wire bonding.

摘要翻译： 引线键合，半导体芯片和半导体封装的方法提供了在芯片的焊盘和基板的接合位置上的导线的针脚结合。 在从毛细管延伸或设置在芯片的接合焊盘上的导线的端部上形成球形针迹。 通过在接合焊盘上压下导线的球，在芯片的接合焊盘上形成球针凸点。 通过按压球形针凸块上的线，在球形针迹上形成线迹的针迹缝合。 毛细管从接合垫移动到接合位置，同时松开电线。 通过在接合位置压下导线，在接合位置形成线的针脚接合，然后与毛细管内的线分离。 引线键合，半导体芯片和半导体封装的方法可以减少或最小化毛细管的移动路径并提供更有效的引线键合。

公开(公告)号：US07521810B2

公开(公告)日：2009-04-21

申请号：US11502427

申请日：2006-08-11

申请人： In-Ku Kang ,  Pyoung-Wan Kim

发明人： In-Ku Kang ,  Pyoung-Wan Kim

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L25/0657 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/78 ,  H01L24/83 ,  H01L24/85 ,  H01L24/91 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/1134 ,  H01L2224/1308 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/83101 ,  H01L2224/83139 ,  H01L2224/83855 ,  H01L2224/8388 ,  H01L2224/85051 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85399 ,  H01L2224/85986 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/15787 ,  H01L2924/20105 ,  H01L2924/351 ,  H01L2224/85186 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/4554

摘要： A chip stack package may include a package substrate, a plurality of semiconductor chips mounted on the package substrate, bonding wires electrically connecting the semiconductor chips to the package substrate, and spacers interposed between the adjacent semiconductor chips. Each of the spacers may include a plurality of metal bumps. The spacers may be higher than the highest point of the bonding wire from the active surface of the semiconductor chip.

摘要翻译： 芯片堆叠封装可以包括封装基板，安装在封装基板上的多个半导体芯片，将半导体芯片电连接到封装基板的接合线以及夹在相邻半导体芯片之间的间隔物。 每个间隔件可以包括多个金属凸块。 间隔物可以高于来自半导体芯片的有源表面的接合线的最高点。

公开(公告)号：US07282431B2

公开(公告)日：2007-10-16

申请号：US11618134

申请日：2006-12-29

申请人： In-Ku Kang ,  Sung-Hwan Yoon

发明人： In-Ku Kang ,  Sung-Hwan Yoon

IPC分类号： H01L21/44 ,  H01L23/495

CPC分类号： H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L29/0657 ,  H01L2224/05647 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/49113 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/10155 ,  H01L2924/10158 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/4554

摘要： A semiconductor package comprises a substrate having connection pads disposed thereon, a semiconductor chip attached to the substrate such that an active surface of the semiconductor chip faces the substrate, and external bonding pads electrically connected to the active surface of the semiconductor chip. The external bonding pads may be formed near the ends of the frame and have an upper surface facing away from the substrate. The external bonding pads are electrically connected with the connection pads.

摘要翻译： 半导体封装包括具有设置在其上的连接焊盘的衬底，附接到衬底的半导体芯片，使得半导体芯片的有源表面面向衬底，以及电连接到半导体芯片的有源表面的外部焊盘。 外部接合焊盘可以形成在框架的端部附近并且具有背离衬底的上表面。 外部接合焊盘与连接焊盘电连接。

公开(公告)号：US20060125093A1

公开(公告)日：2006-06-15

申请号：US11353509

申请日：2006-02-13

申请人： In-Ku Kang ,  Hee-Kook Choi ,  Sang-Ho An ,  Sang-Yeop Lee

发明人： In-Ku Kang ,  Hee-Kook Choi ,  Sang-Ho An ,  Sang-Yeop Lee

IPC分类号： H01L23/34

CPC分类号： H01L24/48 ,  H01L24/45 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48471 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/85399 ,  H01L2224/05599

摘要： Provided herein are multi-chip modules (MCMs) having bonding wires and fabrication methods thereof. The multi-chip module includes a substrate and a plurality of chips sequentially stacked. At least one top chip, stacked above a lowest chip, has an insulating film that covers the backside thereof. Also, each of the stacked chips has bonding pads formed on the periphery or edges of its upper surface. At least one insulator is interposed between the stacked chips. The insulator exposes the pads on the underlying chip. The pads of the respective chips are connected to a set of interconnections, which are disposed on the substrate. This configuration of stacked chips enables the overall height of the memory module to be reduced because the insulating film prevents the bonding wires from contacting the substrate of the top chips.

公开(公告)号：US20050205975A1

公开(公告)日：2005-09-22

申请号：US11077235

申请日：2005-03-11

申请人： In-Ku Kang ,  Seok Goh ,  Jin-Ho Kim ,  Tae-Gyeong Chung ,  Yong-Jae Lee

发明人： In-Ku Kang ,  Seok Goh ,  Jin-Ho Kim ,  Tae-Gyeong Chung ,  Yong-Jae Lee

IPC分类号： H01L25/18 ,  H01L21/301 ,  H01L21/50 ,  H01L21/60 ,  H01L21/78 ,  H01L21/98 ,  H01L23/02 ,  H01L23/12 ,  H01L23/31 ,  H01L25/065 ,  H01L25/07 ,  H01L29/06

CPC分类号： H01L24/32 ,  H01L21/78 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05599 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/49175 ,  H01L2224/4945 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85191 ,  H01L2224/85399 ,  H01L2224/85986 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01057 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10158 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2224/85186 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/4554

摘要： A variety of non-rectangular IC chips having a stepped or modified periphery or edge profile including one or more recessed or indented peripheral regions are provided for incorporation in modified package configurations, single chip packages and multi-chip assemblies, both stacked and/or planar. In the planar configurations, the recessed regions may be utilized, in cooperation with another appropriately sized IC chip, to increase the packing density of the resulting device. Similarly, in the stacked configuration, the recessed regions may be utilized to provide access to bond pads of lower chips and thereby reduce the need for spacers or peripheral thinning techniques and thereby improve the strength of the resulting assembly and/or reduce the overall height of the stacked structure.

摘要翻译： 提供了具有包括一个或多个凹陷或凹入周边区域的阶梯状或改进的周边或边缘轮廓的各种非矩形IC芯片，用于结合到改进的封装结构，单个芯片封装和多芯片组件中，堆叠和/或平面 。 在平面构造中，可以与另一适当尺寸的IC芯片配合使用凹陷区域，以增加所得器件的封装密度。 类似地，在堆叠构造中，凹陷区域可以用于提供对下部芯片的接合焊盘的访问，从而减少对间隔件或外围变薄技术的需要，从而提高所得组件的强度和/或降低总体高度 堆叠结构。

公开(公告)号：US08178393B2

公开(公告)日：2012-05-15

申请号：US12480980

申请日：2009-06-09

申请人： In-Ku Kang

发明人： In-Ku Kang

IPC分类号： H01L21/00

CPC分类号： H01L21/78 ,  H01L21/6836 ,  H01L23/3171 ,  H01L24/48 ,  H01L24/73 ,  H01L2221/68327 ,  H01L2224/02166 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/4899 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor chip, semiconductor package including the same, and a method of manufacturing the semiconductor chip and semiconductor package to block up electrical contacts between bonding wires and the semiconductor chip by providing insulation over the edge of the semiconductor chip.

摘要翻译： 一种半导体芯片，包括该半导体芯片的半导体封装以及通过在半导体芯片的边缘上提供绝缘来制造半导体芯片和半导体封装的方法，以阻断接合线与半导体芯片之间的电接触。

公开(公告)号：US20050039944A1

公开(公告)日：2005-02-24

申请号：US10850864

申请日：2004-05-21

申请人： Jin-Ho Kim ,  In-Ku Kang ,  Hee-Kook Choi

发明人： Jin-Ho Kim ,  In-Ku Kang ,  Hee-Kook Choi

IPC分类号： H01L23/48 ,  H05K3/24 ,  H05K3/34 ,  H05K1/09 ,  H05K1/02

CPC分类号： H05K3/3452 ,  H01L2224/10 ,  H05K3/243 ,  H05K2201/0989 ,  H05K2201/10734 ,  H05K2203/0577 ,  H05K2203/058

摘要： In one embodiment, a pad is formed on a substrate surface. The pad is connected with a connecting pattern. A first mask is formed on the substrate. The first mask has a first opening exposing at least a portion of the pad and a portion of the connecting pattern. A second mask is formed on the first mask. The second mask has a second opening exposing at least a portion of the pad and a portion of the connecting pattern. A boundary surface or sidewall of the first opening is not coplanar with a boundary surface or sidewall of the second opening. Therefore, stresses may be prevented from concentrating on the boundary surface of the first opening, thereby allowing dispersion of the stresses and restraining pattern cracks.

摘要翻译： 在一个实施例中，衬垫形成在衬底表面上。 垫与连接图案连接。 在基板上形成第一掩模。 第一掩模具有暴露焊盘的至少一部分和连接图案的一部分的第一开口。 在第一掩模上形成第二掩模。 第二掩模具有暴露焊盘的至少一部分和连接图案的一部分的第二开口。 第一开口的边界面或侧壁不与第二开口的边界面或侧壁共面。 因此，可以防止应力集中在第一开口的边界面上，从而允许应力分散和约束图案裂纹。

公开(公告)号：US20070108574A1

公开(公告)日：2007-05-17

申请号：US11502427

申请日：2006-08-11

申请人： In-Ku Kang ,  Pyoung-Wan Kim

发明人： In-Ku Kang ,  Pyoung-Wan Kim

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/78 ,  H01L24/83 ,  H01L24/85 ,  H01L24/91 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/1134 ,  H01L2224/1308 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/73207 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/83101 ,  H01L2224/83139 ,  H01L2224/83855 ,  H01L2224/8388 ,  H01L2224/85051 ,  H01L2224/85201 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85399 ,  H01L2224/85986 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/15787 ,  H01L2924/20105 ,  H01L2924/351 ,  H01L2224/85186 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/4554

摘要： A chip stack package may include a package substrate, a plurality of semiconductor chips mounted on the package substrate, bonding wires electrically connecting the semiconductor chips to the package substrate, and spacers interposed between the adjacent semiconductor chips. Each of the spacers may include a plurality of metal bumps. The spacers may be higher than the highest point of the bonding wire from the active surface of the semiconductor chip.

摘要翻译： 芯片堆叠封装可以包括封装基板，安装在封装基板上的多个半导体芯片，将半导体芯片电连接到封装基板的接合线以及夹在相邻半导体芯片之间的间隔物。 每个间隔件可以包括多个金属凸块。 间隔物可以高于来自半导体芯片的有源表面的接合线的最高点。