公开(公告)号：US08563417B2

公开(公告)日：2013-10-22

申请号：US13302219

申请日：2011-11-22

申请人： Jun Lu ,  Alex Niu ,  Yueh-Se Ho ,  Ping Hoang ,  Jacky Gong ,  Yan Xun Xue ,  Xiaolian Zhang ,  Ming-Chen Lu

发明人： Jun Lu ,  Alex Niu ,  Yueh-Se Ho ,  Ping Hoang ,  Jacky Gong ,  Yan Xun Xue ,  Xiaolian Zhang ,  Ming-Chen Lu

IPC分类号： H01L21/78

CPC分类号： H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/3157 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/03009 ,  H01L2224/0332 ,  H01L2224/0384 ,  H01L2224/03848 ,  H01L2224/03849 ,  H01L2224/04034 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05794 ,  H01L2224/058 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06135 ,  H01L2224/06164 ,  H01L2224/06181 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40247 ,  H01L2224/73263 ,  H01L2224/84801 ,  H01L2224/94 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2224/053 ,  H01L2924/014 ,  H01L2924/00

摘要： The invention generally relates to a packaging method of an ultra-thin chip, more specifically, the invention relates to a method for packaging the ultra-thin chip with solder ball thermo-compression in wafer level packaging process. The method starts with disposing solder balls on metal pads arranged on the front surface of semiconductor chips that are formed at the front surface of a semiconductor wafer. The solder balls are soften by heating the wafer, a compression plate is applied with a pressure on the top ends of the solder balls thus forming a co-planar top surface at the top ends of the solder balls. A molding compound is deposited on the front surface of the wafer with the top ends of the solder balls exposed. The wafer is then ground from its back surface to reduce its thickness to achieve ultra-thin chip.

摘要翻译： 本发明一般涉及超薄芯片的封装方法，更具体地说，本发明涉及一种用于在晶片级封装工艺中封装具有焊球热压缩的超薄芯片的方法。 该方法开始于将焊球设置在形成在半导体晶片的前表面的半导体芯片的前表面上的金属焊盘上。 通过加热晶片来软化焊球，压力板在焊球的顶端施加压力，从而在焊球的顶端形成共面顶表面。 模具化合物沉积在晶片的前表面上，其中焊球的顶端被暴露。 然后将晶片从其背面研磨以减小其厚度以实现超薄芯片。

公开(公告)号：US20130130443A1

公开(公告)日：2013-05-23

申请号：US13302219

申请日：2011-11-22

申请人： Jun Lu ,  Alex Niu ,  Yueh-Se Ho ,  Ping Huang ,  Jacky Gong ,  Yan Xun Xue ,  Xiaotian Zhang ,  Ming-Chen Lu

发明人： Jun Lu ,  Alex Niu ,  Yueh-Se Ho ,  Ping Huang ,  Jacky Gong ,  Yan Xun Xue ,  Xiaotian Zhang ,  Ming-Chen Lu

IPC分类号： H01L21/78

CPC分类号： H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/3157 ,  H01L23/49524 ,  H01L23/49562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/03009 ,  H01L2224/0332 ,  H01L2224/0384 ,  H01L2224/03848 ,  H01L2224/03849 ,  H01L2224/04034 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05794 ,  H01L2224/058 ,  H01L2224/0603 ,  H01L2224/06051 ,  H01L2224/06135 ,  H01L2224/06164 ,  H01L2224/06181 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40247 ,  H01L2224/73263 ,  H01L2224/84801 ,  H01L2224/94 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2224/053 ,  H01L2924/014 ,  H01L2924/00

摘要： The invention generally relates to a packaging method of an ultra-thin chip, more specifically, the invention relates to a method for packaging the ultra-thin chip with solder ball thermo-compression in wafer level packaging process. The method starts with disposing solder balls on metal pads arranged on the front surface of semiconductor chips that are formed at the front surface of a semiconductor wafer. The solder balls are soften by heating the wafer, a compression plate is applied with a pressure on the top ends of the solder balls thus forming a co-planar top surface at the top ends of the solder balls. A molding compound is deposited on the front surface of the wafer with the top ends of the solder balls exposed. The wafer is then ground from its back surface to reduce its thickness to achieve ultra-thin chip.

摘要翻译： 本发明一般涉及超薄芯片的封装方法，更具体地说，本发明涉及一种用于在晶片级封装工艺中封装具有焊球热压缩的超薄芯片的方法。 该方法开始于将焊球设置在形成在半导体晶片的前表面的半导体芯片的前表面上的金属焊盘上。 通过加热晶片来软化焊球，压力板在焊球的顶端施加压力，从而在焊球的顶端形成共面顶表面。 模具化合物沉积在晶片的前表面上，其中焊球的顶端被暴露。 然后将晶片从其背面研磨以减小其厚度以实现超薄芯片。

公开(公告)号：US08642385B2

公开(公告)日：2014-02-04

申请号：US13205864

申请日：2011-08-09

申请人： Yan Xun Xue ,  Ping Huang ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Ming-Chen Lu

发明人： Yan Xun Xue ,  Ping Huang ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Ming-Chen Lu

IPC分类号： H01L23/498 ,  H01L21/78

CPC分类号： H01L21/76898 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68377 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/1184 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

摘要： The present invention proposes a package for semiconductor device and the fabrication method for integrally encapsulating a whole semiconductor chip within a molding compound. In the semicondcutor device package, bonding pads distributed on the top of the chip are redistributed into an array of redistributed bonding pads located in an dielectric layer by utilizing the redistribution technique. The electrodes or signal terminals on the top of the semiconductor chip are connected to an electrode metal segment on the bottom of the chip by conductive materials filled in through holes formed in a silicon substrate of a semiconductor wafer. Furthermore, the top molding portion and the bottom molding portion seal the semiconductor chip completely, thus providing optimum mechanical and electrical protections.

摘要翻译： 本发明提出了一种用于半导体器件的封装以及用于将整个半导体芯片整体封装在模塑料中的制造方法。 在半封装器件封装中，通过利用再分配技术，分布在芯片顶部的焊盘重新分布到位于介质层中的再分布焊盘的阵列中。 半导体芯片的顶部上的电极或信号端子通过填充在半导体晶片的硅衬底中形成的通孔中的导电材料连接到芯片底部的电极金属段。 此外，顶部模制部分和底部模制部分完全密封半导体芯片，从而提供最佳的机械和电气保护。

公开(公告)号：US08952509B1

公开(公告)日：2015-02-10

申请号：US14031283

申请日：2013-09-19

申请人： Hamza Yilmaz ,  Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu ,  Xiaotian Zhang ,  Zhi Qiang Niu ,  Ming-Chen Lu ,  Liang Zhao ,  YuPing Gong ,  GuoFeng Lian

发明人： Hamza Yilmaz ,  Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu ,  Xiaotian Zhang ,  Zhi Qiang Niu ,  Ming-Chen Lu ,  Liang Zhao ,  YuPing Gong ,  GuoFeng Lian

IPC分类号： H01L25/07 ,  H01L23/495 ,  H01L25/00

CPC分类号： H01L23/49575 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49551 ,  H01L23/49562 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L2224/37011 ,  H01L2224/371 ,  H01L2224/4007 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/83801 ,  H01L2224/84801 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

摘要： The present invention discloses a stacked dual MOSFET package structure and a preparation method thereof. The stacked dual MOSFET package structure comprises a lead frame unit having a die paddle, a first lead and a second lead; a first chip flipped and attached on a top surface of a main paddle of the die paddle; a second chip attached on a bottom surface of the main paddle; and a metal clip mounted on the back of the flipped first chip and electrically connecting an electrode at the back of the first chip to the first lead. A top surface of a metal bump arranged on each electrode at the front of the second chip, a bottom surface of the die pin of the die paddle, a bottom surface of a lead pin of the second lead, and a bottom surface of the first lead are located on the same plane.

摘要翻译： 本发明公开了一种叠层双MOSFET封装结构及其制备方法。 堆叠双MOSFET封装结构包括具有管芯焊盘，第一引线和第二引线的引线框架单元; 第一芯片翻转并附接在模板的主桨的顶表面上; 附接在主桨的底表面上的第二芯片; 以及安装在翻转的第一芯片的背面上并将第一芯片背面的电极电连接到第一引线的金属夹。 布置在第二芯片的前面的每个电极上的金属凸块的顶表面，模板的模具销的底表面，第二引线的引脚的底表面和第一引脚的底表面 导线位于同一平面上。

公开(公告)号：US20130037935A1

公开(公告)日：2013-02-14

申请号：US13205864

申请日：2011-08-09

申请人： Yan Xun Xue ,  Ping Huang ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Ming-Chen Lu

发明人： Yan Xun Xue ,  Ping Huang ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Ming-Chen Lu

IPC分类号： H01L23/498 ,  H01L21/78

CPC分类号： H01L21/76898 ,  H01L21/561 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2221/6834 ,  H01L2221/68359 ,  H01L2221/68377 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/1184 ,  H01L2224/13009 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

摘要： The present invention relates to a package for semiconductor device and the fabrication method for integrally encapsulating a whole semiconductor chip within a molding compound. In the semicondcutor device package, bonding pads distributed on the top of the chip are redistributed into an array of redistributed bonding pads located in an dielectric layer by utilizing the redistribution technique. The electrodes or signal terminals on the top of the semiconductor chip are connected to an electrode metal segment on the bottom of the chip by conductive materials filled in through holes formed in a silicon substrate of a semiconductor wafer. Furthermore, the top molding portion and the bottom molding portion seal the semiconductor chip completely, thus providing optimum mechanical and electrical protections.

摘要翻译： 本发明涉及一种用于半导体器件的封装以及用于将整个半导体芯片整体封装在模塑料中的制造方法。 在半封装器件封装中，通过利用再分配技术，分布在芯片顶部的焊盘重新分布到位于介质层中的再分布焊盘的阵列中。 半导体芯片的顶部上的电极或信号端子通过填充在半导体晶片的硅衬底中形成的通孔中的导电材料连接到芯片底部的电极金属段。 此外，顶部模制部分和底部模制部分完全密封半导体芯片，从而提供最佳的机械和电气保护。

公开(公告)号：US09214417B2

公开(公告)日：2015-12-15

申请号：US14186275

申请日：2014-02-21

申请人： Yueh-Se Ho ,  Hamza Yilmaz ,  Yan Xun Xue ,  Jun Lu

发明人： Yueh-Se Ho ,  Hamza Yilmaz ,  Yan Xun Xue ,  Jun Lu

IPC分类号： H01L23/495 ,  H01L27/088

CPC分类号： H01L23/49575 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49555 ,  H01L23/49558 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L27/088 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/8485 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

摘要： A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally reducing the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation.

摘要翻译： 组合封装的功率半导体器件包括电连接到管芯焊盘的顶表面的翻转顶部源极低侧MOSFET，第一金属互连板，将高边MOSFET的底部漏极或翻转的高侧MOSFET的顶部源极连接到底部 低端MOSFET的漏极和堆叠在高边MOSFET芯片顶部的第二金属互连板。 高侧，低端MOSFET和IC控制器可以三维封装，减小半导体器件的总体尺寸，并可在相同尺寸的封装内最大化芯片的尺寸，并提高半导体器件的性能。 翻转的低侧MOSFET的顶部源极连接到管芯焊盘的顶表面，并且因此通过裸片的裸露的底表面接地，这简化了裸片焊盘的暴露的底面的形状，并使面积最大化 散热。

公开(公告)号：US08686546B2

公开(公告)日：2014-04-01

申请号：US13077720

申请日：2011-03-31

申请人： Yueh-Se Ho ,  Hamza Yilmaz ,  Yan Xun Xue ,  Jun Lu

发明人： Yueh-Se Ho ,  Hamza Yilmaz ,  Yan Xun Xue ,  Jun Lu

IPC分类号： H01L23/495 ,  H01L23/02

CPC分类号： H01L23/49524 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/84 ,  H01L25/074 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40245 ,  H01L2224/4118 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/8385 ,  H01L2224/8485 ,  H01L2224/85399 ,  H01L2224/92 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/84 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012

摘要： A combined packaged power semiconductor device includes a flipped top source low-side MOSFET electrically connected to a top surface of a die paddle, a first metal interconnection plate connecting between a bottom drain of a high-side MOSFET or a top source of a flipped high-side MOSFET to a bottom drain of the low-side MOSFET, and a second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally that reduces the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation.

摘要翻译： 组合封装的功率半导体器件包括电连接到管芯焊盘的顶表面的翻转顶部源极低侧MOSFET，连接在高侧MOSFET的底部漏极或翻转高电平的顶部源的第一金属互连板 的低端MOSFET的底部漏极和堆叠在高侧MOSFET芯片的顶部上的第二金属互连板。 高侧，低端MOSFET和IC控制器可以三维封装，从而减小半导体器件的总体尺寸，并可在相同尺寸的封装内最大限度地提高芯片的尺寸，并提高半导体器件的性能。 翻转的低侧MOSFET的顶部源极连接到管芯焊盘的顶表面，并且因此通过裸片的裸露的底表面接地，这简化了裸片焊盘的暴露的底面的形状，并使面积最大化 散热。

公开(公告)号：US08564110B2

公开(公告)日：2013-10-22

申请号：US13480391

申请日：2012-05-24

申请人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

发明人： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu ,  Lei Shi ,  Liang Zhao ,  Ping Huang

IPC分类号： H01L23/495

CPC分类号： H01L24/73 ,  H01L23/3107 ,  H01L23/49513 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L24/84 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/05624 ,  H01L2224/06181 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/1184 ,  H01L2224/131 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/16245 ,  H01L2224/2784 ,  H01L2224/291 ,  H01L2224/3015 ,  H01L2224/32245 ,  H01L2224/371 ,  H01L2224/40247 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/83101 ,  H01L2224/83385 ,  H01L2224/83801 ,  H01L2224/84385 ,  H01L2224/84801 ,  H01L2224/8485 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01057 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/16151 ,  H01L2924/167 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/92 ,  H01L2224/83 ,  H01L2224/84 ,  H01L2224/85 ,  H01L2924/00012 ,  H01L2224/48247 ,  H01L2924/01014 ,  H01L2924/00014 ,  H01L2224/73103 ,  H01L2924/00

摘要： A power semiconductor package has an ultra thin chip with front side molding to reduce substrate resistance; a lead frame unit with grooves located on both side leads provides precise positioning for connecting numerous bridge-shaped metal clips to the front side of the side leads. The bridge-shaped metal clips are provided with bridge structure and half or fully etched through holes for relieving superfluous solder during manufacturing process.

摘要翻译： 功率半导体封装具有超薄芯片，具有正面成型以降低基板电阻; 具有位于两侧引线上的凹槽的引线框单元提供精确的定位，用于将多个桥形金属夹连接到侧引线的前侧。 桥形金属夹具有桥结构和半或完全蚀刻的通孔，用于在制造过程中缓解多余的焊料。

公开(公告)号：US08476752B2

公开(公告)日：2013-07-02

申请号：US13494219

申请日：2012-06-12

申请人： Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu

发明人： Yueh-Se Ho ,  Yan Xun Xue ,  Jun Lu

IPC分类号： H01L21/00 ,  H01L23/02

CPC分类号： H01L24/49 ,  H01L23/49524 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/48 ,  H01L2224/371 ,  H01L2224/40095 ,  H01L2224/40137 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/4103 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49111 ,  H01L2224/49112 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01067 ,  H01L2924/01082 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/84

摘要： A package structure for DC-DC converter disclosed herein can reduce the number of encapsulated elements as a low-side MOSFET chip can be stacked above the high-side MOSFET chip of a first die pad, through die pads of different thicknesses or interposers with joint parts of different thicknesses; moreover, it further reduces the size of the entire semiconductor package as a number of bond wires are contained in the space between the controller and the low-side MOSFET chip. Moreover, electrical connection between the top source electrode pin and the bottom source electrode pin of the low-side MOSFET chip is realized with a metal joint plate, such that when the DC-DC converter is sealed with plastic, the metal joint plate can be exposed outside to improve the thermal performance and effectively reduce the thickness of the semiconductor package.

摘要翻译： 本文公开的用于DC-DC转换器的封装结构可以减少封装元件的数量，因为低侧MOSFET芯片可以堆叠在第一裸片焊盘的高侧MOSFET芯片上方，通过具有不同厚度的芯片焊盘或具有接头的插入件 不同厚度的零件; 而且，由于控制器和低侧MOSFET芯片之间的空间中包含多个接合线，因此进一步减小了整个半导体封装的尺寸。 此外，利用金属接合板实现了顶部源极电极引脚和低端MOSFET芯片的底部源极电极引脚之间的电连接，使得当DC-DC转换器用塑料密封时，金属接合板可以 暴露在外面以改善热性能并有效地减小半导体封装的厚度。

公开(公告)号：US08436429B2

公开(公告)日：2013-05-07

申请号：US13118445

申请日：2011-05-29

申请人： Yan Xun Xue ,  Yueh-Se Ho ,  Lei Shi ,  Jun Lu ,  Liang Zhao

发明人： Yan Xun Xue ,  Yueh-Se Ho ,  Lei Shi ,  Jun Lu ,  Liang Zhao

IPC分类号： H01L27/088

CPC分类号： H01L23/49562 ,  H01L23/49524 ,  H01L23/49575 ,  H01L24/48 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A stacked power semiconductor device includes vertical metal oxide semiconductor field-effect transistors and dual lead frames packaged with flip-chip technology. In the method of manufacturing the stacked power semiconductor device, a first semiconductor chip is flip chip mounted on the first lead frame. A mounting clips is connected to the electrode at back side of the first semiconductor chip. A second semiconductor chip is mounted on the second lead frame, which is then flipped and stacked on the mounting clip.

摘要翻译： 叠层功率半导体器件包括垂直金属氧化物半导体场效应晶体管和采用倒装芯片技术封装的双引线框架。 在制造堆叠式功率半导体器件的方法中，第一半导体芯片是安装在第一引线框上的倒装芯片。 安装夹在第一半导体芯片的背面连接到电极。 第二半导体芯片安装在第二引线框架上，然后翻转并堆叠在安装夹上。