公开(公告)号：US09875992B2

公开(公告)日：2018-01-23

申请号：US14821767

申请日：2015-08-09

Applicant: Junyeong Heo ,  Chajea Jo ,  Taeje Cho

Inventor： Junyeong Heo ,  Chajea Jo ,  Taeje Cho

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L23/544 ,  H01L25/065 ,  H01L25/00 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/544 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L24/94 ,  H01L25/50 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/5448 ,  H01L2224/0361 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/1403 ,  H01L2224/14131 ,  H01L2224/14136 ,  H01L2224/14177 ,  H01L2224/14179 ,  H01L2224/14505 ,  H01L2224/14519 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/1703 ,  H01L2224/17051 ,  H01L2224/17177 ,  H01L2224/17181 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32148 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/8113 ,  H01L2224/83104 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06589 ,  H01L2225/06593 ,  H01L2924/15311 ,  H01L2924/3512 ,  H01L2224/03 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/17136 ,  H01L2224/17179

Abstract: An embodiment includes a semiconductor package comprising: a substrate; a first semiconductor chip mounted on the substrate; a second semiconductor chip mounted on a top surface of the first semiconductor chip; a connecting bump disposed between the first and second semiconductor chips to electrically connect the second semiconductor chip to the first semiconductor chip; and a first heat dissipation part disposed on the top surface of the first semiconductor chip between the first and second semiconductor chips and spaced apart from a bottom surface of the second semiconductor chip.

公开(公告)号：US10186500B2

公开(公告)日：2019-01-22

申请号：US15357741

申请日：2016-11-21

Applicant: Seung-Kwan Ryu ,  Yonghwan Kwon ,  Yun Seok Choi ,  Chajea Jo ,  Taeje Cho

Inventor： Seung-Kwan Ryu ,  Yonghwan Kwon ,  Yun Seok Choi ,  Chajea Jo ,  Taeje Cho

IPC: H01L25/10 ,  H01L25/00

Abstract: A semiconductor package includes upper and lower semiconductor chip packages, and a redistribution wiring layer pattern interposed between the packages. The lower package includes a molding layer in which at least one chip is embedded, and has a top surface and an inclined sidewall surface along which the redistribution wiring layer pattern is formed. The upper and lower packages are electrically connected to through the redistribution wiring layer pattern. A first package may be formed by a wafer level packaging technique and may include a redistribution wiring layer as a substrate, a semiconductor chip disposed on the redistribution wiring layer, and a molding layer on which the lower package, redistribution wiring layer pattern and upper package are disposed.

公开(公告)号：US10192855B2

公开(公告)日：2019-01-29

申请号：US14841736

申请日：2015-09-01

Applicant: Sunkyoung Seo ,  Chajea Jo ,  Ji Hwang Kim ,  Taeje Cho

Inventor： Sunkyoung Seo ,  Chajea Jo ,  Ji Hwang Kim ,  Taeje Cho

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L25/10 ,  H01L23/367 ,  H01L23/13 ,  H01L23/36 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/18

Abstract: A semiconductor package is provided. The semiconductor package include a lower semiconductor package including a lower package substrate and a lower semiconductor chip mounted thereon, and an upper semiconductor package provided on the lower semiconductor package to include an upper package substrate and an upper semiconductor chip mounted thereon. The upper package substrate include an upper heat-dissipation pattern, the lower semiconductor chip include a first via connected to the upper heat-dissipation pattern through the lower semiconductor chip, and the first via may provide a pathway for dissipating heat generated in the lower semiconductor chip.

公开(公告)号：US09461029B2

公开(公告)日：2016-10-04

申请号：US14744031

申请日：2015-06-19

Applicant: Hye-young Jang ,  Chang-Seong Jeon ,  Chajea Jo ,  Taeje Cho

Inventor： Hye-young Jang ,  Chang-Seong Jeon ,  Chajea Jo ,  Taeje Cho

IPC: H01L21/50 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/1412 ,  H01L2224/1413 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17104 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/321 ,  H01L2224/32145 ,  H01L2224/33181 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/83191 ,  H01L2224/83203 ,  H01L2224/83379 ,  H01L2224/92 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014

Abstract: A semiconductor package may include a first semiconductor chip including a first surface facing a package substrate, a second surface opposite to the first surface, and at least one through-electrode penetrating the first semiconductor chip, a molding layer molding the first semiconductor chip and exposing the second surface of the first semiconductor chip, a second semiconductor chip stacked on the second surface of the first semiconductor chip, and a non-conductive film provided between the first and second semiconductor chips. The second semiconductor chip includes an overhang portion extending past an edge of the first semiconductor chip. For example, a size of the second semiconductor chip may be greater than that of the first semiconductor chip, so the second semiconductor chip has an overhang. The second semiconductor chip includes at least one interconnecting terminal electrically connected to the at least one through-electrode.

Abstract translation: 半导体封装可以包括第一半导体芯片，其包括面向封装基板的第一表面，与第一表面相对的第二表面，以及穿透第一半导体芯片的至少一个贯通电极，模制第一半导体芯片的模制层和暴露 第一半导体芯片的第二表面，堆叠在第一半导体芯片的第二表面上的第二半导体芯片，以及设置在第一和第二半导体芯片之间的非导电膜。 第二半导体芯片包括延伸穿过第一半导体芯片的边缘的突出部分。 例如，第二半导体芯片的尺寸可以大于第一半导体芯片的尺寸，因此第二半导体芯片具有突出端。 第二半导体芯片包括电连接到至少一个通孔的至少一个互连端子。

公开(公告)号：US08026592B2

公开(公告)日：2011-09-27

申请号：US12408369

申请日：2009-03-20

Applicant: Minseung Yoon ,  Namseog Kim ,  Pyoungwan Kim ,  Keumhee Ma ,  Chajea Jo

Inventor： Minseung Yoon ,  Namseog Kim ,  Pyoungwan Kim ,  Keumhee Ma ,  Chajea Jo

IPC: H01L23/04

CPC classification number: H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00

Abstract: Through-Silicon-Via (TSV) structures can include a conductive via through a substrate extending from an upper surface of the substrate to a backside surface of the substrate opposite the upper surface, a conductive protective layer including Ni and/or Co can be at a bottom of the conductive via, and a separate polymer insulating layer can be on the backside surface of the substrate in contact with the conductive protective layer.

Abstract translation: 通过硅 - 通（TSV）结构可以包括通过从衬底的上表面延伸到衬底的与上表面相对的背面的衬底的导电通孔，包括Ni和/或Co的导电保护层可以在 导电通孔的底部和单独的聚合物绝缘层可以在与导电保护层接触的基板的背面上。

公开(公告)号：US08129840B2

公开(公告)日：2012-03-06

申请号：US12503274

申请日：2009-07-15

Applicant: Chajea Jo ,  Uihyoung Lee ,  Jae-hyun Phee ,  Jeong-Woo Park ,  Ha-Young Yim

Inventor： Chajea Jo ,  Uihyoung Lee ,  Jae-hyun Phee ,  Jeong-Woo Park ,  Ha-Young Yim

IPC: H01L21/48

CPC classification number: H01L21/563 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/1146 ,  H01L2224/11472 ,  H01L2224/11505 ,  H01L2224/11902 ,  H01L2224/11912 ,  H01L2224/13027 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/14104 ,  H01L2224/1411 ,  H01L2224/14131 ,  H01L2224/17107 ,  H01L2224/73204 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01105 ,  H01L2924/014 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor package and a method of manufacturing the semiconductor package. The semiconductor package include a substrate including a plurality of pads and a plurality of bumps evenly disposed on an entire region of the substrate regardless of an arrangement of the plurality of pads. According to the present invention, a simplification of a process can be accomplished, a cost of a process can be reduced, reliability can be improved and an under-filling can become easy.

Abstract translation: 半导体封装以及半导体封装的制造方法。 半导体封装包括基板，其包括多个焊盘和均匀地设置在基板的整个区域上的多个凸块，而与多个焊盘的布置无关。 根据本发明，可以实现工艺的简化，可以降低工艺成本，可以提高可靠性，并且能够容易地进行填充不足。

公开(公告)号：US20110318917A1

公开(公告)日：2011-12-29

申请号：US13163284

申请日：2011-06-17

Applicant: Minseung Yoon ,  Namseog Kim ,  Pyoungwan Kim ,  Keumhee Ma ,  Chajea Jo

Inventor： Minseung Yoon ,  Namseog Kim ,  Pyoungwan Kim ,  Keumhee Ma ,  Chajea Jo

IPC: H01L21/768

CPC classification number: H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00

Abstract: Through-Silicon-Via (TSV) structures can be provided by forming a conductive via through a substrate extending from an upper surface of the substrate to a backside surface of the substrate, that is opposite the upper surface, and having a conductive protective layer comprising Ni and/or Co formed at a bottom of the conductive via. A polymer insulating layer can be formed on the backside surface that is separate from the substrate and in contact with the conductive protective layer.

Abstract translation: 可以通过从衬底的上表面延伸到基板的与该上表面相对的背面表面延伸的衬底形成导电通孔，并且具有导电保护层，该导电保护层包括 Ni和/或Co形成在导电通孔的底部。 聚合物绝缘层可以形成在与基板分离并与导电保护层接触的背面上。

公开(公告)号：US20100038800A1

公开(公告)日：2010-02-18

申请号：US12408369

申请日：2009-03-20

Applicant: Minseung Yoon ,  Namseog Kim ,  Pyoungwan Kim ,  Keumhee Ma ,  Chajea Jo

Inventor： Minseung Yoon ,  Namseog Kim ,  Pyoungwan Kim ,  Keumhee Ma ,  Chajea Jo

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02372 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/05557 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01327 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/014 ,  H01L2924/00

Abstract: Through-Silicon-Via (TSV) structures can include a conductive via through a substrate extending from an upper surface of the substrate to a backside surface of the substrate opposite the upper surface, a conductive protective layer including Ni and/or Co can be at a bottom of the conductive via, and a separate polymer insulating layer can be on the backside surface of the substrate in contact with the conductive protective layer.

Abstract translation: 通过硅 - 通（TSV）结构可以包括通过从衬底的上表面延伸到衬底的与上表面相对的背面的衬底的导电通孔，包括Ni和/或Co的导电保护层可以在 导电通孔的底部和单独的聚合物绝缘层可以在与导电保护层接触的基板的背面上。