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    SEMICONDUCTOR MEMORY DEVICE HAVING IMPROVED VOLTAGE TRANSMISSION PATH AND DRIVING METHOD THEREOF
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE HAVING IMPROVED VOLTAGE TRANSMISSION PATH AND DRIVING METHOD THEREOF 有权
    具有改进的电压传输路径的半导体存储器件及其驱动方法

    公开(公告)号：US20100102434A1

    公开(公告)日：2010-04-29

    申请号：US12652875

    申请日：2010-01-06

    申请人： Sun-Won Kang ,  Seung-Duk Baek

    发明人： Sun-Won Kang ,  Seung-Duk Baek

    IPC分类号： H01L25/16 ,  H01L23/498

    CPC分类号： G11C5/063 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

    摘要： Provided are a semiconductor memory device and a method of driving the device which can improve a noise characteristic of a voltage signal supplied to a memory cell of the device. The semiconductor memory device includes a first semiconductor chip and one or more second semiconductor chips stacked on the first chip. The first chip includes an input/output circuit for sending/receiving a voltage signal, a data signal, and a control signal to/from an outside system. The one or more second semiconductor chips each include a memory cell region for storing data. The second semiconductor chips receive at least one signal through one or more signal paths that are formed outside the input/output circuit of the first chip.

    摘要翻译： 提供一种半导体存储器件和驱动器件的方法，该器件可以改善提供给器件的存储单元的电压信号的噪声特性。 半导体存储器件包括第一半导体芯片和堆叠在第一芯片上的一个或多个第二半导体芯片。 第一芯片包括用于向/从外部系统发送/接收电压信号，数据信号和控制信号的输入/输出电路。 一个或多个第二半导体芯片各自包括用于存储数据的存储单元区域。 第二半导体芯片通过形成在第一芯片的输入/输出电路外部的一个或多个信号路径接收至少一个信号。

    Stack package
    7.
    发明申请
    Stack package 有权
    堆栈包

    公开(公告)号：US20100090326A1

    公开(公告)日：2010-04-15

    申请号：US12588382

    申请日：2009-10-14

    申请人： Seung-Duk Baek ,  Sun-Won Kang ,  Jong-Joo Lee

    发明人： Seung-Duk Baek ,  Sun-Won Kang ,  Jong-Joo Lee

    IPC分类号： H01L25/065

    CPC分类号： H01L25/0657 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： A stack package may include a substrate having first and second faces opposite each other and an opening formed therein. The first semiconductor chip may be mounted on the first face of the substrate and include a through electrode in the middle region of the first semiconductor chip that is exposed through the opening. The second semiconductor chip may be stacked on the first semiconductor chip and electrically connected to the first semiconductor chip by the through electrode of the first semiconductor chip. The circuit pattern may be formed on the second face of the substrate and include a bonding pad arranged adjacent to the opening and electrically connected to the through electrode of the first semiconductor chip through the opening, an outer connection pad spaced apart from the bonding pad and a connection wiring extending from the opening to the outer connection pad via the bonding pad.

    摘要翻译： 堆叠包装可以包括具有彼此相对的第一和第二面以及其中形成的开口的衬底。 第一半导体芯片可以安装在基板的第一面上，并且在通过开口暴露的第一半导体芯片的中间区域中包括通孔。 第二半导体芯片可以堆叠在第一半导体芯片上并且通过第一半导体芯片的通孔电连接到第一半导体芯片。 电路图案可以形成在基板的第二面上，并且包括邻近开口布置的焊盘，并且通过开口电连接到第一半导体芯片的通孔，与焊盘间隔开的外连接焊盘和 连接配线，从连接焊盘的开口延伸到外部连接焊盘。

    TEST PROBE FOR SEMICONDUCTOR PACKAGE
    8.
    发明申请
    TEST PROBE FOR SEMICONDUCTOR PACKAGE 失效
    半导体封装的测试探针

    公开(公告)号：US20070139062A1

    公开(公告)日：2007-06-21

    申请号：US11677017

    申请日：2007-02-20

    申请人： Sun-Won Kang

    发明人： Sun-Won Kang

    IPC分类号： G01R31/02

    CPC分类号： G01R1/06733 ,  G01R1/06738

    摘要： An embodiment may comprise a test probe to measure electrical properties of a semiconductor package having ball-shaped terminals. The probe may include a signal tip and a ground tip. The signal tip may have a spherical lower surface allowing good contact with a ball-shaped signal terminal. The ground tip may be extended from a lower end of a ground barrel that encloses the signal tip. The ground tip may move independent of the signal tip by means of a barrel stopper and a spring. Thus, the probe can be used regardless of the size of and the distance between the package terminals.

    摘要翻译： 实施例可以包括用于测量具有球形端子的半导体封装的电特性的测试探针。 探头可以包括信号尖端和接地尖端。 信号尖端可以具有允许与球形信号端子良好接触的球形下表面。 接地尖端可以从包围信号尖端的接地筒的下端延伸。 接地尖端可以通过镜筒塞和弹簧独立于信号尖端移动。 因此，可以使用探针，而不管封装端子之间的尺寸和距离。

    Three-dimensional semiconductor module having multi-sided ground block
    9.
    发明申请
    Three-dimensional semiconductor module having multi-sided ground block 有权
    具有多面接地块的三维半导体模块

    公开(公告)号：US20070001282A1

    公开(公告)日：2007-01-04

    申请号：US11369444

    申请日：2006-03-06

    申请人： Sun-Won Kang ,  Seung-Duk Baek

    发明人： Sun-Won Kang ,  Seung-Duk Baek

    IPC分类号： H01L23/52

    CPC分类号： G11C5/04 ,  B81B7/0074 ,  H01L23/3677 ,  H01L23/467 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/5385 ,  H01L23/5387 ,  H01L25/065 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/15192 ,  H01L2924/19107 ,  H05K1/189 ,  H05K3/0061 ,  H05K2201/056

    摘要： The present invention relates to a three-dimensional semiconductor module having at least one unit semiconductor device connected to the outer-facing side surfaces of a multi-side ground block. The unit semiconductor device has a structure in which a semiconductor package (or semiconductor chip) is mounted on a unit wiring substrate. Ground pads to be connected to the outer-facing side surfaces of the ground block are formed on the first surface of the unit wiring substrate, the semiconductor chip is mounted on the second surface opposite to the first surface, and contact terminals electrically connected to the semiconductor chip are formed on the second surface.

    摘要翻译： 本发明涉及一种三维半导体模块，其具有连接到多侧接地块的面向外侧面的至少一个单元半导体器件。 单元半导体器件具有半导体封装（或半导体芯片）安装在单元布线基板上的结构。 在单元布线基板的第一表面上形成要连接到接地块的面向外侧的接地焊盘，半导体芯片安装在与第一表面相对的第二表面上，并且接触端子电连接到 半导体芯片形成在第二表面上。

    Wafer-level stack package
    10.
    发明授权
    Wafer-level stack package 有权
    晶圆级堆栈包

    公开(公告)号：US08153521B2

    公开(公告)日：2012-04-10

    申请号：US12962934

    申请日：2010-12-08

    申请人： Sun-Won Kang ,  Seung-Duk Baek

    发明人： Sun-Won Kang ,  Seung-Duk Baek

    IPC分类号： H01L21/50

    CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05009 ,  H01L2224/05548 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2224/05599 ,  H01L2224/05099

    摘要： A wafer-level stack package includes semiconductor chips, first connection members, a second connection member, a substrate and an external connection terminal. The semiconductor chips have a power/ground pad and a signal pad. The first connection members are electrically connected to the power/ground pad and the signal pad of each of the semiconductor chips. The second connection member is electrically connected to at least one of the power/ground pads of each of the semiconductor chips, the power/ground pads being connected to the first connection members. The substrate supports the stacked semiconductor chips, the substrate including wirings that are electrically connected to the first connection members and the second connection member. The external connection terminal is provided on a surface of the substrate opposite to a surface where the semiconductor chips are stacked, wherein the external connection terminals are electrically connected to the wirings, respectively.

    摘要翻译： 晶圆级堆叠封装包括半导体芯片，第一连接构件，第二连接构件，基板和外部连接端子。 半导体芯片具有电源/接地焊盘和信号焊盘。 第一连接构件电连接到电源/接地焊盘和每个半导体芯片的信号焊盘。 第二连接构件电连接到每个半导体芯片的功率/接地焊盘中的至少一个，电源/接地焊盘连接到第一连接构件。 基板支撑层叠的半导体芯片，基板包括电连接到第一连接构件和第二连接构件的布线。 外部连接端子设置在与半导体芯片堆叠的表面相对的表面上，其中外部连接端子分别电连接到布线。