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    PACKAGE ASSEMBLY CONFIGURATIONS FOR MULTIPLE DIES AND ASSOCIATED TECHNIQUES
    3.
    发明申请
    PACKAGE ASSEMBLY CONFIGURATIONS FOR MULTIPLE DIES AND ASSOCIATED TECHNIQUES 审中-公开
    多组合和相关技术的封装组装配置

    公开(公告)号：US20150014852A1

    公开(公告)日：2015-01-15

    申请号：US13941322

    申请日：2013-07-12

    申请人： Yueli Liu ,  Islam A. Salama ,  Mihir K. Roy ,  Ram S. Viswanath

    发明人： Yueli Liu ,  Islam A. Salama ,  Mihir K. Roy ,  Ram S. Viswanath

    IPC分类号： H01L23/498 ,  H01L23/00

    CPC分类号： H01L23/49811 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/00

    摘要： Embodiments of the present disclosure are directed towards package assembly configurations for multiple dies and associated techniques. In one embodiment, a package assembly includes a package substrate having a first side and a second side disposed opposite to the first side, a first die mounted on the first side and electrically coupled with the package substrate by one or more first die-level interconnects, a second die mounted on the second side and electrically coupled with the package substrate by one or more second die-level interconnects and package-level interconnect structures disposed on the first side of the package substrate and configured to route electrical signals between the first die and an electrical device external to the package substrate and between the second die and the external device. Other embodiments may be described and/or claimed.

    摘要翻译： 本公开的实施例涉及用于多个管芯和相关技术的封装组装构造。 在一个实施例中，封装组件包括具有第一侧和与第一侧相对设置的第二侧的封装衬底，第一裸片安装在第一侧上并且通过一个或多个第一裸片级互连与封装衬底电耦合 ，安装在所述第二侧上的第二裸片，并且通过设置在所述封装衬底的所述第一侧上的一个或多个第二管芯级互连和封装级互连结构与所述封装衬底电耦合，并且被配置为将所述第一管芯 以及在封装衬底外部以及第二管芯和外部器件之间的电器件。 可以描述和/或要求保护其他实施例。

    INTERCONNECT STRUCTURES FOR EMBEDDED BRIDGE
    5.
    发明申请
    INTERCONNECT STRUCTURES FOR EMBEDDED BRIDGE 有权
    嵌入桥的互连结构

    公开(公告)号：US20150028486A1

    公开(公告)日：2015-01-29

    申请号：US13951122

    申请日：2013-07-25

    申请人： Yueli Liu ,  Chong Zhang ,  Qinglei Zhang

    发明人： Yueli Liu ,  Chong Zhang ,  Qinglei Zhang

    IPC分类号： H01L23/48 ,  H01L21/50

    CPC分类号： H01L23/48 ,  H01L21/50 ,  H01L23/49811 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/16 ,  H01L2224/131 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2924/12042 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K1/185 ,  H05K2201/10674 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

    摘要： Embodiments of the present disclosure are directed towards interconnect structures for embedded bridge in integrated circuit (IC) package assemblies. In one embodiment, a method includes depositing an electrically insulative layer on a bridge interconnect structure, the bridge interconnect structure including a die contact that is configured to route electrical signals between a first die and a second die, depositing a sacrificial layer on the electrically insulative layer, forming an opening through the sacrificial layer and the electrically insulative layer to expose the die contact and forming a die interconnect of the first die or the second die by depositing an electrically conductive material into the opening. Other embodiments may be described and/or claimed.

    摘要翻译： 本公开的实施例涉及用于集成电路（IC）封装组件中的嵌入式桥的互连结构。 在一个实施例中，一种方法包括在桥互连结构上沉积电绝缘层，所述桥互连结构包括被配置为在第一管芯和第二管芯之间布置电信号的管芯接触件，在电绝缘层上沉积牺牲层 形成穿过所述牺牲层和所述电绝缘层的开口，以暴露所述管芯接触，并通过将导电材料沉积到所述开口中而形成所述第一管芯或所述第二管芯的管芯互连。 可以描述和/或要求保护其他实施例。

    CORELESS SUBSTRATE WITH PASSIVE DEVICE PADS
    7.
    发明申请
    CORELESS SUBSTRATE WITH PASSIVE DEVICE PADS 有权
    无源基板与被动设备垫

    公开(公告)号：US20140268612A1

    公开(公告)日：2014-09-18

    申请号：US13801822

    申请日：2013-03-13

    申请人： Qinglei Zhang ,  Yueli Liu

    发明人： Qinglei Zhang ,  Yueli Liu

    IPC分类号： H01L23/492

    CPC分类号： H01L23/492 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L25/16 ,  H01L28/60 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2924/12042 ,  H01L2924/15311 ,  H05K3/4682 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/00

    摘要： Embodiments of the present disclosure are directed towards coreless substrates with passive device pads, as well as methods for forming coreless substrates with passive device pads and package assemblies and systems incorporating such coreless substrates. A coreless substrate may comprise a plurality of build-up layers, such as bumpless build-up layers (BBUL). In various embodiments, electrical routing features and passive device pads may be disposed on an outer surface of the substrate. In various embodiments, the passive device pads may be coupled with a conductive element disposed on or within the build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power between the passive device pads and a die coupled to the coreless substrate.

    摘要翻译： 本公开的实施例涉及具有无源器件焊盘的无芯基板，以及用于形成具有无源器件焊盘和封装组件的无芯衬底以及包含这种无芯衬底的系统的方法。 无芯衬底可以包括多个堆积层，例如无凸起积聚层（BBUL）。 在各种实施例中，电路由特征和无源器件焊盘可设置在衬底的外表面上。 在各种实施例中，无源器件焊盘可以与布置在积层层上或内部的导电元件耦合。 在各种实施例中，可以在多个堆积层中限定电路径，以在无源器件焊盘与耦合到无芯衬底之间的管芯之间布置电力。