摘要:
A package-on-package (“PoP”) structure and a method of forming are provided. The PoP structure may be formed by forming a first set of electrical connections on a first substrate. A first material may be applied to the first set of electrical connections. A second substrate may be provided having a second set of electrical connections formed thereon. The first set of electrical connections of the first substrate having the epoxy flux applied may be contacted to the second electrical connections of the second substrate. A reflow process may be performed to electrically connect the first substrate to the second substrate. The epoxy flux applied to the first electrical connections of the first substrate may prohibit electrical bridges or shorts from forming during the reflow process.
摘要:
A package-on-package (“PoP”) structure and a method of forming are provided. The PoP structure may be formed by forming a first set of electrical connections on a first substrate. A first material may be applied to the first set of electrical connections. A second substrate may be provided having a second set of electrical connections formed thereon. The first set of electrical connections of the first substrate having the epoxy flux applied may be contacted to the second electrical connections of the second substrate. A reflow process may be performed to electrically connect the first substrate to the second substrate. The epoxy flux applied to the first electrical connections of the first substrate may prohibit electrical bridges or shorts from forming during the reflow process.
摘要:
A semiconductor device assembly includes a substrate having an area of the surface treated to form a surface roughness. A die is mounted on the substrate by a plurality of coupling members. An underfill substantially fills a gap disposed between the substrate and the die, wherein a fillet width of the underfill is substantially limited to the area of surface roughness.
摘要:
The present disclosure relates to a tool arrangement and method to reduce warpage within a package-on-package semiconductor structure, while minimizing void formation within an electrically-insulating adhesive which couples the packages. A pressure generator and a variable frequency microwave source are coupled to a process chamber which encapsulates a package-on-package semiconductor structure. The package-on-package semiconductor structure is simultaneously heated by the variable frequency microwave source at variable frequency, variable temperature, and variable duration and exposed to an elevated pressure by the pressure generator. This combination for microwave heating and elevated pressure limits the amount of warpage introduced while preventing void formation within an electrically-insulating adhesive which couples the substrates of the package-on-package semiconductor structure.
摘要:
A method includes dispensing an underfill between a first package component and a second package component, wherein the first package component is placed on a lower jig, and the second package component is over and bonded to the first package component. A through-opening is in the lower jig and under the first package component. The underfill is cured, wherein during the step of curing the underfill, a force is applied to flatten the first package component. The force is applied by performing an action selected from the group consisting of vacuuming and air blowing through the through-opening.
摘要:
A method includes loading a first package component on a concave boat, and placing a second package component over the first package component. A load clamp is placed over the second package component, wherein the load clamp is supported by a temperature-variable spacer of the concave boat. A reflow step is performed to bond the second package component to the first package component. During a temperature-elevation step of the reflow step, the temperature-variable spacer is softened in response to an increase in temperature, and a height of the softened temperature-variable spacer is reduced, until the load clamp is stopped by a rigid spacer of the concave boat.
摘要:
A method includes applying a polymer-comprising material over a carrier, and forming a via over the carrier. The via is located inside the polymer-comprising material, and substantially penetrates through the polymer-comprising material. A first redistribution line is formed on a first side of the polymer-comprising material. A second redistribution line is formed on a second side of the polymer-comprising material opposite to the first side. The first redistribution line is electrically coupled to the second redistribution line through the via.
摘要:
A system and method for forming contacts is provided. An embodiment comprises forming the contacts on a substrate and then coining the contacts by physically shaping them using, e.g., a molding chamber. The physical shaping of the contacts may be performed using a patterned portion of the molding chamber or else by placing a patterned stencil around the contacts prior before a force is applied to physically reshape the contacts. The contacts may be reshaped into a cylindrical, oval, cuboid, or rectangular shape, for example.
摘要:
A device includes a package component having conductive features on a top surface, and a polymer region molded over the top surface of the first package component. A plurality of openings extends from a top surface of the polymer region into the polymer region, wherein each of the conductive features is exposed through one of the plurality of openings. The plurality of openings includes a first opening having a first horizontal size, and a second opening having a second horizontal size different from the first horizontal size.
摘要:
Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL.