摘要:
An electronic device including electronic circuit structures formed with an electrically conductive adhesive (ECA) with low and stable contact resistance including at least one melt-processable reactive resin, at least one reactive diluent, at least one rheological additive, at least one curing agent, at least one organic acid catalyst, and copper particles. The ECA is useful for filling vias, and bonding together components of electronic circuit structures.
摘要:
An electronic device including electronic circuit structures formed with an electrically conductive adhesive (ECA) with low and stable contact resistance including at least one melt-processable reactive resin, at least one reactive diluent, at least one rheological additive, at least one curing agent, at least one organic acid catalyst, and copper particles. The ECA is useful for filling vias, and bonding together components of electronic circuit structures.
摘要:
An electrically conductive adhesive (ECA) with low and stable contact resistance includes at least one melt-processable reactive resin, at least one reactive diluent, at least one rheological additive, copper particles, at least one curing agent and at least one organic acid catalyst. The ECA is useful for filling vias, and bonding together components of electronic circuit structures.
摘要:
A process for preparing an electrically conductive adhesive (ECA) with low and stable contact resistance by mixing at least one melt-processable reactive resin, at least one reactive diluent, at least one rheological additive, at least one curing agent, at least one organic acid catalyst, and copper particles. The ECA is useful for filling vias, and bonding together components of electronic circuit structures.
摘要:
Fan-Out Wafer Level Packages (FO-WLPs) and methods for fabricating FO-WLPs having Embedded Ground Plane (EGP) connections are provided. In one embodiment, the method includes forming a molded panel around an EGP array from which a plurality of preformed EGP connections project. One or more Redistribution Layers (RDLs) are produced over the molded panel. The molded panel is then singulated to yield a plurality of FO-WLPs each including a molded package body containing an EGP from the EGP array and one or more of preformed EGP connections.
摘要:
A method for fabricating a stacked microelectronic device includes attaching a first package layer to a second package layer to form stacked microelectronic layers. Saw streets of the first package layer overlie and are aligned with saw streets of the second package layer. The first and second package layers include respective edge connectors formed between the saw streets and electronic components in the first and second package layers. A through package via is formed in one of the saw streets of the first and second package layers. The via is filled with conductive material. The stacked package layers are singulated along the saw streets in a manner that retains a portion of the conductive material to form a sidewall connector between at least two of the edge connectors.
摘要:
An electrical component package is disclosed comprising: an electrical component having an embedded surface, a structure attached to the electrical component opposite the embedded surface, a conductive adhesive directly attached to the embedded surface, where the conductive adhesive is shaped to taper away from the embedded surface, and an encapsulation material covering the conductive adhesive and the electrical component. In various embodiments, the tapered conductive adhesive facilitates the securing of the conductive adhesive to the electrical component by the encapsulation material. Also disclosed are various methods of forming an electrical component package having a single interface conductive interconnection on the embedded surface. The conductive interconnection is configured to maintain an interconnection while under stress forces. Further disclosed in a method of applied a conductive adhesive that enables design flexibility regarding the shape and depth of the conductive interconnection.
摘要:
Methods for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging a plurality of microelectronic device panels in a panel stack. Each microelectronic device panel contains plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are created in the panel stack exposing the plurality of package edge conductors, and a plurality of sidewall conductors is formed interconnecting different ones of the package edge conductors exposed through the trenches. The panel stack is then separated into a plurality of stacked microelectronic packages each including at least two microelectronic devices electrically interconnected by at least one of the plurality of sidewall conductors included within the stacked microelectronic package.
摘要:
An electronic fabrication process and structure is provided for attaching discrete passive surface mount devices (SMD) to a substrate in a single step. A liquid noflow resin encapsulant containing flux material is dispensed between presoldered pads on a substrate. The SMD, having a pair of electrical contacts, is pressed into said encapsulant so that the electrical contacts make contact with said presoldered pads. Heat is applied to first activate said flux material and then reflow the solder on said presoldered pads to bond said SMD contacts to said presoldered pads. The reflow temperature is maintained for about 180 seconds during which time the resin solidifies. The resin encapsulant fills the space between substrate and SMD and forms fillets around the solder bonded contacts.
摘要:
A method and structure for solderably coupling a semiconductor chip to a substrate, with an underfill between the chip and the substrate. In forming the structure, underfill material is dispensed upon a conductive pad on the substrate. The underfill material comprises a resin and a filler. The filler density is less than the resin density. The chip is moved toward the substrate and into the underfill until a solder member coupled to the chip is proximate the conductive pad. The structure is heated, resulting in soldering the solder member to the conductive pad and in curing the underfill. Filler particles move through the resin and toward the chip, resulting in an increased filler concentration near the solder member, and a reduced underfill coefficient of thermal expansion (CTE) near the solder member that is close to the CTE of the solder member.