公开(公告)号：US07024695B1

公开(公告)日：2006-04-04

申请号：US09476737

申请日：1999-12-30

Applicant: Mohan J. Kumar ,  Arvind Kumar

Inventor： Mohan J. Kumar ,  Arvind Kumar

IPC: G06F11/00 ,  G06F11/22 ,  G06F11/30 ,  G06F11/32 ,  G06F11/34 ,  G06F11/36 ,  G06F12/14 ,  G06F12/16 ,  G06F15/18 ,  G08B23/00

CPC classification number: G06F21/31 ,  G06F11/0748 ,  G06F11/0793 ,  G06F21/305 ,  G06F2221/2103 ,  H04L41/00 ,  H04L41/22 ,  H04L63/083

Abstract: To prevent unauthorized access to hardware management information in an out-of-band mode, i.e., when the operating system of the hardware is not executing, a method and apparatus employ an authentication protocol. Upon receiving a request for hardware component information in a service processor that is disposed in a hardware component, which request is received as an open session request and which request passes external to an operating system controlling the hardware component, the service processor transmits a challenge string to the requesting client application. In response to a challenge response received from the requesting client application, the service processor compares the challenge response to an expected response to the challenge. The expected challenge response is calculated by the service processor. Based on the result of the comparison, the service processor transmits an authentication response to the requesting client application indicating success or failure of the authentication process. On the client side, in response to a challenge string from the service processor, the requesting client application transmits to the service processor a challenge response, which includes an sequence number that increments with every new message from the requesting client application. The challenge response also includes a hash number calculated by the requesting client application, which hash number is a function of the challenge string, session identification number, sequence number and/or a password. Each new packet including data and/or commands from the client application includes a similarly calculated hash number.

Abstract translation: 为了防止在带外模式（即，硬件的操作系统未执行）下的硬件管理信息的未经授权的访问，方法和装置采用认证协议。 在接收到在硬件组件中设置的服务处理器中的硬件组件信息的请求时，该请求作为开放会话请求被接收，并且哪个请求在控制硬件组件的操作系统外部通过，服务处理器发送挑战串 到请求的客户端应用程序。 响应于从请求客户端应用程序接收到的挑战响应，服务处理器将挑战响应与对挑战的期望响应进行比较。 预期的挑战响应由服务处理器计算。 基于比较的结果，服务处理器向请求客户端应用发送认证响应，指示认证过程的成败。 在客户端，响应于来自服务处理器的挑战串，请求客户端应用程序向服务处理器发送挑战响应，该响应响应包括随请求的客户端应用程序的每个新消息递增的序列号。 挑战响应还包括由请求客户端应用计算的哈希号，该哈希号是挑战串，会话识别号，序列号和/或密码的函数。 包括来自客户端应用程序的数据和/或命令的每个新分组包括类似地计算的散列数。

公开(公告)号：US20210096848A1

公开(公告)日：2021-04-01

申请号：US17120072

申请日：2020-12-11

Applicant: Sarathy Jayakumar ,  Chuan Song ,  Mohan J. Kumar

Inventor： Sarathy Jayakumar ,  Chuan Song ,  Mohan J. Kumar

IPC: G06F8/656 ,  G06F9/48 ,  G06F9/4401 ,  G06F9/455 ,  G06F12/1027

Abstract: A microcode (uCode) hot-upgrade method for bare metal cloud deployment and associated apparatus. Under the uCode hot-upgrade method, a uCode path is received at an out-of-band controller (e.g., baseboard management controller (BMC)) and buffered in a memory buffer in the out-of-band controller. The out-of-band controller exposes the memory buffer as a Memory-Mapped Input-Output (MMIO) range to a host CPU. A uCode upgrade interrupt service is triggered to upgrade uCode for one or more CPUs in a bare-metal cloud platform during runtime of a tenant host operating system (OS) using an out-of-bound process. This innovation enables cloud service providers to deploy uCode hot-patches to bare metal servers for live-patch without touching the tenant operating system environment.

公开(公告)号：US20200285461A1

公开(公告)日：2020-09-10

申请号：US16841410

申请日：2020-04-06

Applicant: Mohan J. Kumar ,  Sarathy Jayakumar ,  Chuan Song ,  Ruixia Li ,  Xiaojin Yuan ,  Haiyue Wang ,  Chong Han

Inventor： Mohan J. Kumar ,  Sarathy Jayakumar ,  Chuan Song ,  Ruixia Li ,  Xiaojin Yuan ,  Haiyue Wang ,  Chong Han

IPC: G06F8/656 ,  G06F8/654 ,  G06F9/4401 ,  G06F9/445

Abstract: A microcode (uCode) hot-upgrade method for bare metal cloud deployment and associated apparatus. The uCode hot-upgrade method applies a uCode patch to a firmware storage device (e.g., BIOS SPI flash) through an out-of-band controller (e.g., baseboard management controller (BMC)). In conjunction with receiving a uCode patch, a uCode upgrade interrupt service is triggered to upgrade uCode for one or more CPUs in a bare-metal cloud platform during runtime of a tenant host operating system (OS) using an out-of-bound process. This innovation enables cloud service providers to deploy uCode hot-patches to bare metal servers for persistent storage and live-patch without touching the tenant operating system environment.

公开(公告)号：US10223204B2

公开(公告)日：2019-03-05

申请号：US13994609

申请日：2011-12-22

Applicant: Theodros Yigzaw ,  Geeyarpuram N. Santhanakrishnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

Inventor： Theodros Yigzaw ,  Geeyarpuram N. Santhanakrishnan ,  Ganapati N. Srinivasa ,  Jose A. Vargas ,  Hisham Shafi ,  Michael Mishaeli ,  Ehud Cohen ,  Zeev Sperber ,  Shlomo Raikin ,  Mohan J. Kumar ,  Julius Y. Mandelblat

IPC: G06F11/00 ,  G06F11/14 ,  G06F11/10

Abstract: An apparatus and method are described for detecting and correcting data fetch errors within a processor core. For example, one embodiment of an instruction processing apparatus for detecting and recovering from data fetch errors comprises: at least one processor core having a plurality of instruction processing stages including a data fetch stage and a retirement stage; and error processing logic in communication with the processing stages to perform the operations of: detecting an error associated with data in response to a data fetch operation performed by the data fetch stage; and responsively performing one or more operations to ensure that the error does not corrupt an architectural state of the processor core within the retirement stage.

公开(公告)号：US20180089130A1

公开(公告)日：2018-03-29

申请号：US15274656

申请日：2016-09-23

Applicant: Sheshaprasad G. Krishnapura ,  Vipul Lal ,  Mohan J. Kumar ,  Shaji Kootaal Achuthan ,  Ty H. Tang

Inventor： Sheshaprasad G. Krishnapura ,  Vipul Lal ,  Mohan J. Kumar ,  Shaji Kootaal Achuthan ,  Ty H. Tang

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/36 ,  G06F13/42 ,  G06F11/30

Abstract: A selectively upgradeable disaggregated server is generally described herein. An example modular server unit, the modular server unit includes a processor module coupled to an input/output (I/O) module via a connector. The processor module to communicate with the I/O module via the connector to store and retrieve data. The processor module is a separate hardware unit from the I/O module.

公开(公告)号：US20170289256A1

公开(公告)日：2017-10-05

申请号：US15089377

申请日：2016-04-01

Applicant: Mohan J. Kumar ,  Murugasamy K. Nachimuthu

Inventor： Mohan J. Kumar ,  Murugasamy K. Nachimuthu

IPC: H04L29/08 ,  H04L29/06 ,  H04L12/24 ,  H04L12/46 ,  H04L12/931

CPC classification number: H04L67/125 ,  G06F1/20 ,  H04L12/4641 ,  H04L41/0668 ,  H04L41/0695 ,  H04L41/12 ,  H04L43/08 ,  H04L43/0817 ,  H04L43/10 ,  H04L49/70 ,  H04L63/08 ,  H04L67/02 ,  H04L67/10 ,  H04L67/1095 ,  H04L67/1097 ,  H04L67/12 ,  H04L69/40

Abstract: Methods and apparatus for highly available rack management in Rack Scale environment. Rack Management Modules (RMMs) are configured to manage power and thermal zones in a rack including a plurality of pooled system drawers, wherein each pooled system drawer is associated with a respective power zone including power sensors and power control devices and a respective thermal zone including thermal sensors and thermal devices. During operation, one of the RMMs is implemented as a master RMM, and the other is implemented as a slave RMM. The master RMM is used to monitor the power and thermal zones. State information is periodically synchronized between the master RMM and the slave RMM. The RMMs are further configured to perform a fail-over operation in connection with a failed or failing RMM, where after the fail-over operation the slave becomes the new master RMM and the previous master RMM becomes the new slave.

公开(公告)号：US20150186215A1

公开(公告)日：2015-07-02

申请号：US14142726

申请日：2013-12-27

Applicant: Debendra Das Sharma ,  Mohan J. Kumar ,  Balin T. Fleischer

Inventor： Debendra Das Sharma ,  Mohan J. Kumar ,  Balin T. Fleischer

IPC: G06F11/10 ,  G06F11/20

CPC classification number: G06F11/2094 ,  G06F11/108 ,  G06F11/1088 ,  G06F11/2043 ,  G06F11/2087 ,  G06F11/2092 ,  G06F11/2097 ,  G06F12/08 ,  G06F12/0833 ,  G06F12/0837 ,  G06F15/16 ,  G06F2201/805 ,  G06F2201/82

Abstract: An apparatus for coherent shared memory across multiple clusters is described herein. The apparatus includes a fabric memory controller and one or more nodes. The fabric memory controller manages access to a shared memory region of each node such that each shared memory region is accessible using load store semantics, even in response to failure of the node. The apparatus also includes a global memory, wherein each shared memory region is mapped to the global memory by the fabric memory controller.

Abstract translation: 本文描述了跨多个集群的相干共享存储器的装置。 该装置包括织物存储器控制器和一个或多个节点。 织物存储器控制器管理对每个节点的共享存储器区域的访问，使得即使响应于节点的故障，每个共享存储器区域也可以使用加载存储器语义来访问。 该设备还包括全局存储器，其中每个共享存储器区域被结构存储器控制器映射到全局存储器。

公开(公告)号：US20150089287A1

公开(公告)日：2015-03-26

申请号：US14127548

申请日：2013-09-23

Applicant: Sarathy Jayakumar ,  Mohan J. Kumar ,  Krishnakanth V. Sistla

Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Krishnakanth V. Sistla

IPC: G06F11/07 ,  G06F13/24 ,  G06F11/30 ,  G06F12/08 ,  G06F11/16 ,  G06F1/30

CPC classification number: G06F11/079 ,  G06F1/30 ,  G06F11/14 ,  G06F11/1441 ,  G06F11/165 ,  G06F11/2015 ,  G06F11/3031 ,  G06F11/3072 ,  G06F12/0802 ,  G06F12/0804 ,  G06F13/24 ,  G06F2201/86

Abstract: An event management resource monitors a processor environment. In response to detecting occurrence of a trigger event in the processor environment, the event management resource initiates a transfer of processor cache data from volatile storage in the processor environment to non-volatile memory. The event management resource can be configured to produce status information associated with the transfer of cache data to a respective non-volatile memory resource. The event management resource stores the status information in a non-volatile storage resource for later retrieval. Accordingly, status information associated with the event causing the transfer is available for analysis on subsequent power up or reboot of a respective computer system.

Abstract translation: 事件管理资源监视处理器环境。 响应于在处理器环境中检测到触发事件的发生，事件管理资源启动处理器高速缓存数据从处理器环境中的易失性存储器传送到非易失性存储器。 可以将事件管理资源配置为产生与缓存数据传送相关联的状态信息到相应的非易失性存储器资源。 事件管理资源将状态信息存储在非易失性存储资源中，供以后检索。 因此，与导致传送的事件相关联的状态信息可用于在随后的相应计算机系统的加电或重新启动时进行分析。

公开(公告)号：US20140181576A1

公开(公告)日：2014-06-26

申请号：US13722499

申请日：2012-12-20

Applicant: Sudip S. Chahal ,  Mohan J. Kumar ,  Don G. Meyers ,  David Stanasolovich ,  Joshua Boelter

Inventor： Sudip S. Chahal ,  Mohan J. Kumar ,  Don G. Meyers ,  David Stanasolovich ,  Joshua Boelter

IPC: G06F9/455 ,  G11B20/18

CPC classification number: G06F9/45533 ,  G06F9/45558 ,  G06F9/50 ,  G06F9/5016 ,  G06F12/06 ,  G06F2009/45583 ,  G06F2212/152

Abstract: Apparatuses and methods associated with memory allocations for virtual machines are disclosed. In embodiments, an apparatus may include a processor; a plurality of memory modules; and a memory controller configured to provide a layout of the memory modules. The apparatus may further include a VMM configured to be operated by the processor to manage execution of a VM by the processor including selective allocation of the memory modules to the VM using the layout of the memory modules provided to the VMM by the memory controller. Other embodiments may be described and claimed.

Abstract translation: 公开了与虚拟机的存储器分配相关联的装置和方法。 在实施例中，装置可以包括处理器; 多个存储器模块; 以及存储器控制器，被配置为提供所述存储器模块的布局。 该设备可以进一步包括被配置为由处理器操作以管理由处理器执行VM的VMM，包括使用由存储器控制器提供给VMM的存储器模块的布局来将存储器模块选择性地分配给VM。 可以描述和要求保护其他实施例。

公开(公告)号：US20140129767A1

公开(公告)日：2014-05-08

申请号：US13997189

申请日：2011-09-30

Applicant: Raj K Ramanujan ,  Rajat Agarwal ,  Kai Cheng ,  Taarinya Polepeddi ,  Camille C. Raad ,  David J. Zimmerman ,  Muthukumar P. Swaminathan ,  Dimitrios Ziakas ,  Mohan J. Kumar ,  Bassam N. Coury ,  Glenn N. Hinton

Inventor： Raj K Ramanujan ,  Rajat Agarwal ,  Kai Cheng ,  Taarinya Polepeddi ,  Camille C. Raad ,  David J. Zimmerman ,  Muthukumar P. Swaminathan ,  Dimitrios Ziakas ,  Mohan J. Kumar ,  Bassam N. Coury ,  Glenn N. Hinton

IPC: G06F12/08 ,  G11C14/00 ,  G11C11/406

CPC classification number: G06F12/0811 ,  G06F12/0895 ,  G06F12/0897 ,  G06F2212/2024 ,  G06F2212/205 ,  G11C11/40615 ,  G11C14/009 ,  Y02D10/13

Abstract: A system and method are described for integrating a memory and storage hierarchy including a non-volatile memory tier within a computer system. In one embodiment, PCMS memory devices are used as one tier in the hierarchy, sometimes referred to as “far memory.” Higher performance memory devices such as DRAM placed in front of the far memory and are used to mask some of the performance limitations of the far memory. These higher performance memory devices are referred to as “near memory.”

Abstract translation: 描述了用于集成包括计算机系统内的非易失性存储器层的存储器和存储层级的系统和方法。 在一个实施例中，PCMS存储器件被用作层次结构中的一层，有时被称为“远存储器”。更高性能的存储器件例如放置在远存储器之前的DRAM，并用于掩盖某些性能限制 远记忆 这些更高性能的存储器件被称为“接近存储器”。